CS5014 datasheet(15/40 Pages) CIRRUS

15 / 40 page

Also, the CS5012A/14/16’s internal RC oscillator

exhibits jitter (typically

± 0.05% of its period),

which is high compared to crystal oscillators. If

the CS5012A/14/16 is configured for synchro-

nous sampling while operating from its internal

oscillator, this jitter will directly affect sampling

purity. The user can obtain best sampling purity

while synchronously sampling by using an exter-

nal crystal-based clock.

Reset

Upon power up, the CS5012A/14/16 must be re-

set to guarantee a consistent starting condition

and initially calibrate the devices. Due to the

CS5012A/14/16’s low power dissipation and low

temperature drift, no warm-up time is required

before reset to accommodate any self-heating ef-

fects. However, the voltage reference input

should have stabilized to within 5%, 1% or

0.25% of its final value, for the CS5012A/14/16

respectively, before RST falls to guarantee an ac-

curate calibration. Later, the CS5012A/14/16 may

be reset at any time to initiate a single full cali-

bration. Reset overrides all other functions. If

reset, the CS5012A/14/16 will clear and initiate a

new calibration cycle mid-conversion or mid-cali-

bration.

Resets can be initiated in hardware or software.

The sim p lest m ethod of resetting the

CS5012A/14/16 involves strobing the RST pin

high for at least 100 ns. When RST is brought

high all internal logic clears. When it returns low,

a full calibration begins which takes 58,280

CLKIN cycles for the CS5012A (approximately

9.1 ms with a 6.4 MHz clock) and 1,441,020

CLKIN cycles for the CS5016 and CS5014.

(approximately 360 ms with a 4 MHz

CLKIN). A simple power-on reset circuit can be

built using a resistor and capacitor, and a

Schmitt-trigger inverter to prevent oscillation (see

Figure 6). The CS5012A/14/16 can also be reset

in software when under microprocessor control.

The CS5012A/14/16 will reset whenever CS, A0,

and HOLD are taken low simultaneously. See the

Microprocessor Interface section (below) to

eliminate the possibility of inadvertent software

reset. The EOC output remains high throughout

the calibration operation and will fall upon its

completion. It can thus be used to generate an

interrupt indicating the CS5012A/14/16 is ready

for operation. While calibrating, the HOLD input

is ignored until EOC falls. After EOC falls, six

CLKIN cycles plus 2.25

µs (1.32 µs for the

CS5012A -7 version only) must be allowed for

signal acquisition before HOLD is activated. Un-

der microprocessor-independent operation (CS,

RD low; A0 high) the CS5014’s and CS5016’s

EOC output will not fall at the completion of the

calibration cycle, but EOT will fall 15 CLKIN

cycles later.

Initiating Calibration

All modes of calibration can be controlled in

hardware or software. Accuracy can thereby be

insured at any time or temperature throughout op-

erating life. After initial calibration at power-up,

the CS5012A/14/16’s charge-redistribution design

yields better temperature drift and more graceful

aging than resistor-based technologies, so calibra-

tion is normally only required once, after

power-up.

The first mode of calibration, reset, results in a

single full calibration cycle. The second type of

calibration, "burst" cal, allows control of partial

calibration cycles.

Due to an unforeseen con-

didtion inside the part, asynchronous termination

of calibration may result in a sub-optimal result.

Burst cal should not be used.

+5V

RST

CS5012A/14/16

Figure 6. Power-on Reset Circuit

CS5012A, CS5014, CS5016

DS14F8

2-21

CS5012A CS5014 CS5016

DS14F9

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