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AM29PDLI27H датащи(PDF) 51 Page - SPANSION

номер детали AM29PDLI27H
подробное описание детали  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
PDF  68 Pages
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AM29PDLI27H датащи(HTML) 51 Page - SPANSION

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June 30, 2003
Am29PDL127H
49
ADV ANCE
I N FO RMAT I O N
AC CHARACTERISTIC
Read-Only Operations
Notes:
1.
Not 100% tested.
2.
See Figure 10 and Table 16 for test specifications
3.
Measurements performed by placing a 50 ohm termination on the
data pin with a bias of VCC/2. The time from OE# high to the data
bus driven to V
CC/2 is taken as tDF.
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
53
63
68
83, 88
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
55
65
85
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
556585
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
556585
ns
t
PACC
Page Access Time
Max
20
253030ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
20
25
30
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 3)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Notes 3)
Min
5
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns



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