ISL6535

FN9255 Rev 3.00

Page 2 of 15

March 3, 2016

Pin Descriptions

PIN #

SOIC

PIN #

QFN

PIN NAME

DESCRIPTION

1

14

RT

this pin to GND, the switching frequency is set from between 200kHz and 1.5MHz according

Equation 1:

Alternately ISL6535’s switching frequency can be lowered from 200kHz to 50kHz by

connecting the RT pin with a resistor to VCC according to Equation 2:

2

15

OCSET

The current limit is programmed by connecting this pin with a resistor and capacitor to the

drain of the high-side MOSEFT. A 200µA current source develops a voltage across the

resistor, which is then compared with the voltage developed across the high-side MOSFET. A

blanking period of 120ns is provided for noise immunity.

3

1

SS

Connect a capacitor from this pin to ground. This capacitor, along with an internal 30µA

current source, sets the soft-start interval of the converter.

4

2

COMP

COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting

input of the error amplifier and the COMP pin is the error amplifier output. These pins are

used to compensate the voltage-control feedback loop of the converter.

53

FB

6

4

EN

This pin is a TTL compatible input. Pull this pin below 0.8V to disable the converter. In

shutdown the soft-start pin is discharged and the UGATE and LGATE pins are held low.

7

6

GND

Signal ground for the IC. All voltage levels are measured with respect to this pin.

8

7

PHASE

This pin connects to the source of the high-side MOSFET and the drain of the low-side

MOSFET. This pin represents the return path for the high-side gate driver. During normal

switching, this pin is used for high-side current sensing.

9

8

UGATE

Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper

MOSFET.

10

9

BOOT

This pin provides bias to the upper MOSFET driver. A bootstrap circuit may be used to create

a BOOT voltage suitable to drive a standard N-channel MOSFET.

11

10

PGND

This is the power ground connection. Tie the lower MOSFET source and board ground to this

pin.

12

11

LGATE

Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower

MOSFET.

13

12

PVCC

Provide a 12V ±10% bias supply for the lower gate drive to this pin. This pin should be

bypassed with a capacitor to PGND.

14

13

VCC

Provide a 12V bias supply for the chip to this pin. The pin should be bypassed with a capacitor

to GND.

-

5

REFIN

Upon enable if REFIN is less than 2.2V, the external reference pin is used as the control

reference instead of the internal 0.597V reference. An internal 6µA pull-up to 5V is provided

for disabling this functionality.

-

16

SSDONE

Provides an open-drain signal at the end of soft-start.

-

PAD

EPAD

The exposed pad is at GND potential, but does not conduct current; the GND and PGND pins

must be used for bias current. The pad should be tied to a GND plane with as many thermal

vias as possible, for optimal thermal performance.



6500

 200 kHz



–

------------------------------------------------------- 1.3k



–



(EQ. 1)



55000

200 kHz

 F



–

------------------------------------------------------- 70k



+



(EQ. 2)