ISL6535CBZ datasheet(10/15 Pages) RENESAS

10 / 15 page

ISL6535

FN9255 Rev 3.00

Page 10 of 15

March 3, 2016

Compensating the Converter

The ISL6535 Single-phase converter is a voltage-mode controller.

This section highlights the design consideration for a voltage-mode

controller requiring external compensation. To address a broad

range of applications, a type-3 feedback network is

recommended (see Figure 9).

Figure 10 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage is

regulated to the reference voltage level. The error amplifier

output is compared with the oscillator triangle wave to provide a

pulse-width modulated wave with an amplitude of VIN at the

PHASE node. The PWM wave is smoothed by the output filter. The

output filter capacitor bank’s equivalent series resistance is

represented by the series resistor ESR.

The modulator transfer function is the small-signal transfer

function of VOUT/VCOMP. This function is dominated by a DC gain

and shaped by the output filter, with a double pole break

frequency at FLC and a zero at FCE. For the purpose of this

analysis, L and DCR represent the output inductance and its

DCR, while C and ESR represents the total output capacitance

and its equivalent series resistance.

The compensation network consists of the error amplifier

(internal to the ISL6535) and the external R1 to R3, C1 to C3

components. The goal of the compensation network is to provide

a closed loop transfer function with high 0dB crossing frequency

(F0; typically 0.1 to 0.3 of fSW) and adequate phase margin

(better than 45°). Phase margin is the difference between the

closed loop phase at F0dB and 180°. The equations that follow

relate the compensation network’s poles, zeros and gain to the

components (R1, R2, R3, C1, C2 and C3) in Figures 9 and 10.

Use the following guidelines for locating the poles and zeros of

the compensation network:

1. Select a value for R1 (1kΩ to 10kΩ, typically). Calculate value

for R2 for desired converter bandwidth (F0). If setting the

output voltage to be equal to the reference set voltage, as

shown in Figure 10, the design procedure can be followed as

presented.

As the ISL6535 supports 100% duty cycle, DMAX equals 1.

The ISL6535 uses a fixed ramp amplitude (VOSC) of 1.9V,

Equation 8 simplifies to Equation 9:

2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,

at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor in

Equation 10 to the desired number). The higher the quality

factor of the output filter and/or the higher the ratio FCE/FLC,

the lower the FZ1 frequency (to maximize phase boost at FLC).

3. Calculate C2 such that FP1 is placed at FCE.

4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such

that FP2 is placed below fSW (typically, 0.3 to 1.0 times fSW).

fSW represents the switching frequency of the regulator.

Change the numerical factor (0.7) below to reflect desired

placement of this pole. Placement of FP2 lower in frequency

helps reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at the

COMP pin and minimizing resultant duty cycle jitter.

It is recommended that a mathematical model be used to plot

the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

frequency response of the modulator (GMOD), feedback

compensation (GFB) and closed-loop response (GCL):

COMPENSATION BREAK FREQUENCY EQUATIONS

Figure 11 on page 11 shows an asymptotic plot of the DC/DC

converter’s gain vs frequency. The actual Modulator Gain has a

high gain peak dependent on the quality factor (Q) of the output

filter, which is not shown. Using the previously mentioned

guidelines should yield a compensation gain similar to the curve

plotted. The open loop error amplifier gain bounds the

compensation gain. Check the compensation gain at FP2 against

the capabilities of the error amplifier. The closed loop gain, GCL,

is constructed on the log-log graph of Figure 11 by adding the

modulator gain, GMOD (in dB), to the feedback compensation

gain, GFB (in dB). This is equivalent to multiplying the modulator

transfer function and the compensation transfer function and

then plotting the resulting gain.

FLC





---------------------------

FCE

 C ESR



---------------------------------

(EQ. 7)

VOSC R1 F0



DMAX VIN FLC



----------------------------------------------

(EQ. 8)

1.9 R1 F0



VIN FLC



-------------------------------

(EQ. 9)

 R

2 0.5 FLC





-----------------------------------------------

(EQ. 10)

 R

2 C1 FCE

–



--------------------------------------------------------

(EQ. 11)

fSW

FLC

----------- 1

–

--------------------

 R

3 0.7 fSW





-----------------------------------------------

(EQ. 12)

GMOD f

DMAX VIN



VOSC

-------------------------------

1s f

 ESR C



1s f

 ESR DCR

 C



2 f LC



-----------------------------------------------------------------------------------------------------------



GFB f

1s f

 R

2 C1



 R

C1 C2





----------------------------------------------------



1s f

 R

 C



1s f

 R

3 C3



 1s f

 R

C1 C2



C1 C2

---------------------

















-------------------------------------------------------------------------------------------------------------------------

GCL f

GMOD f GFB f



where s f





 fj



(EQ. 13)

FZ1

 R

2 C1



-------------------------------

FZ2

 R

 C



-------------------------------------------------

FP1

 R

C1 C2



C1 C2

---------------------



---------------------------------------------

FP2

 R

3 C3



-------------------------------

(EQ. 14)

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