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PEF82913 датащи(PDF) 25 Page - Infineon Technologies AG

номер детали PEF82913
подробное описание детали  2B1Q Second Gen. Modular ISDN NT
PDF  240 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEF82913 датащи(HTML) 25 Page - Infineon Technologies AG

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PEF 82912/82913
Overview
Data Sheet
11
2001-03-30
10
WR
R/W
I
I
Write
Indicates a write access to the registers (Intel
bus mode).
Read/Write
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host
access as a write operation (Motorola bus
mode).
9
ALE
I
Address Latch Enable
An address on the external address/data bus
(multiplexed bus type only) is latched with the
falling edge of ALE.
ALE also selects the microcontroller interface
type (multiplexed or non multiplexed).
5
RST
I
Reset:
Low active reset input. Schmitt-Trigger input
with hysteresis of typical 360 mV. Tie to ’1’ if not
used.
6
RSTO
OD
Reset Output:
Low active reset output.
15
INT
OD
Interrupt Request:
INT becomes active if the Q-SMINT®I requests
an interrupt.
18
MCLK
O
Microcontroller Clock:
Clock output for the microcontroller
19
Tie to ‘1‘
20
EAW
I
External Awake:
A low level on EAW during power down
activates the clock generation of the Q-
SMINT®I, i.e. the IOM®-2 interface provides
FSC, DCL and BCL for read and write
access.1)
43
SX1
O
S-Bus Transmitter Output (positive)
44
SX2
O
S-Bus Transmitter Output (negative)
47
SR1
I
S-Bus Receiver Input
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function



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