PEF22504HT datasheet(102/255 Pages) INFINEON

102 / 255 page

QuadLIU

PEF 22504

Functional Description

Data Sheet

102

Rev. 1.3, 2006-01-25

3.9

Transmit Path

The transmit path of the QuadLIU

TM is shown in Figure 36.

Figure 36

Transmit System of one Channel

The serial transmit bit stream (single rail or dual rail) is processed by the transmitter which has the following

functions:

•

AIS generation (blue alarm)

•

Generation of In-band loop-up/-down code

3.9.1

Transmit Line Interface

The transmit line interface includes two integrated serial resistors R

TX as shown in Figure 37. Two application

modes are possible:

•

For non-generic applications the extermal serial resistance R

SER is dependent on the operation mode

(E1/T1/J1) as shown in Table 28. The additional register bit PC6.TSRE is not used, R

TX is always 2 Ω

•

For generic E1/T1/J1 applications with optimized return loss the transmit output resistance R

TX is configured

by the register bit PC6.TSRE: The operation mode (E1/T1/J1) is selected by software without the need for

external hardware changes: Here the external resistor R

SER is always 0 Ω, see Table 28.

In E1 mode the value of R

SER in Table 28 is valid for both characteristic line impedances Z0 = 120 Ω and Z0 = 75 Ω.

Note that shorts between XL1 and XL2 cannot be detected, because the short circuit current is lower than 120 mA.

This way a short between XL1 and XL2 will not harm the device

The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the

appropriate programmable shape. The unipolar data is provided on pin XDI and the digital transmitter.

Pulse

Shaper,

LBO

Encoder

XDIP

XCLK

XL2

DCO-X

Dual Transmit Elastic Buffer

MCLK

QLIU_ITS10305

Transmit Line

Interface

E: controlledby CMR2.IXSC andCMR2.IRSC

F: controlledby CMR1.DXSSand automatic transmit clock switching

G: controlledby LIM1.RL,JATT andLIM2.ELT

H: controlledby DIC1.XBS(1:0) andautomatic transmit clock switching

%: divider: controlledby CMR6.STF(2:0)

Master

Clocking Unit

DAC

XL1/XOID

FCLKR

TCLK

FCLKX

Automatic Transmit

Clock Switching

recovered

receive clock

internal

transmit

clock

from

DCO-R

(in)

XL4

XL3

XDIN

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