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R1LP0408CSB-5SC датащи(PDF) 12 Page - Renesas Technology Corp |
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R1LP0408CSB-5SC датащи(HTML) 12 Page - Renesas Technology Corp |
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12 / 14 page ![]() R1LP0408C-C Series Rev.2.00, May.26.2004, page 12 of 12 Low VCC Data Retention Characteristics (Ta = −20 to +70°C) Parameter Symbol Min Typ Max Unit Test conditions* 3 VCC for data retention VDR 2 V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V to +70 °C ICCDR 8 µA VCC = 3.0 V, Vin ≥ 0 V to +40 °C ICCDR 1.0* 2 3 µA CS# ≥ VCC − 0.2 V −5SC to +25 °C ICCDR 0.8* 1 3 µA to +70 °C ICCDR 16 µA to +40 °C ICCDR 1.0* 2 10 µA Data retention current −7LC to +25 °C ICCDR 0.8* 1 10 µA Chip deselect to data retention time tCDR 0 ns See retention waveform Operation recovery time tR tRC* 4 ns Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25 °C and specified loading, and not guaranteed. 2. Typical values are at VCC = 3.0 V, Ta = +40 °C and specified loading, and not guaranteed. 3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high impedance state. 4. tRC = read cycle time. Low VCC Data Retention Timing Waveform (CS# Controlled) V CC 4.5 V 2.2 V 0 V CS# t CDR t R CS# ≥ V CC – 0.2 V V DR Data retention mode |
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