R1LP0408CSB-5SC datasheet(8/14 Pages) RENESAS

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R1LP0408C-C Series

Rev.2.00, May.26.2004, page 8 of 12

Write Cycle

R1LP0408C-C

-5SC

-7LC

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write cycle time

tWC



Chip selection to end of write

tCW



Address setup time

tAS



Address valid to end of write

tAW



Write pulse width

tWP



3, 12

Write recovery time

tWR



Write to output in high-Z

tWHZ

1, 2, 7

Data to write time overlap

tDW



Data hold from write time

tDH



Output active from end of write

tOW



Output disable to output in high-Z

tOHZ

1, 2, 7

Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later

transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going

high or WE# going high. tWP is measured from the beginning of write to the end of write.

4. tCW is measured from CS# going low to the end of write.

5. tAS is measured from the address valid to the beginning of write.

6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.

7. During this period, I/O pins are in the output state so that the input signals of the opposite phase

to the outputs must not be applied.

8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#

transition, the output remain in a high impedance state.

9. Dout is the same phase of the write data of this write cycle.

10. Dout is the read data of next address.

11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of

the opposite phase to the outputs must not be applied to them.

12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of

data bus contention. tWP

≥ tDW min + tWHZ max

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