MP2681BGS datasheet(20/23 Pages) MPS

20 / 23 page

MP2681B – CC/CV CONTROLLER WITH FULL PROTECTION

MP2681B Rev.1.0

www.MonolithicPower.com

12/22/2014

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

APPLICATION INFORMATION

COMPONENT SELECTION

Setting the VDD Voltage

VDD voltage is regulated based on the battery

specifications, according to the ID resistor.

Refer to Table 1 for the relationship between the

ID voltage and the VDD voltage.

Setting the Charge Current

The current limitation (ICHG) is performed by

sensing the voltage across the sense resistor RS

and comparing it to the charge-current reference

(VIREF), refer to formula (1):

CHG

IREF

(1)

The charge-current reference is controlled by CR

to set the charge rate. If CR is logic high, VIREF is

fixed at 0.16V internally. Pull CR low to set the

charger in slow-charge (VIREF is set to 0.016V).

Timer Setting

TMR is used to set the internal oscillator

frequency. Refer to timer-setting formulas below:

Pre-charge timer

TPre-1P(s)= 34560×C(uF)

(2)

Total-charge timer:

Fast charge:

TTotal-1P-fast(s)= 69120×C(uF)

(3)

Slow charge:

TTotal-1P-slow(s)= 276480×C(uF)

(4)

Choosing the Resistor for NTC Sensor

Figure 9 shows an internal resistor-divider

reference circuit to limit the four temperature

thresholds at 90%·LDO, 77%·LDO, 32%·LDO,

and 25%·LDO, respectively (to specify operation

under cold, cool, warm, and hot conditions). For

a given NTC thermistor, select appropriate RT1

and RT2 to set the NTC window:

LDO

//R

NTC_Cold

(5)

77%

LDO

//R

NTC_Cool

(6)

32%

LDO

//R

NTC_Warm

(7)

25%

LDO

//R

NTC_Hot

(8)

RNTC_Hot is the value of the NTC resistor at the

highest temperature of the required temperature-

operation range. RNTC_Cold is the value of the NTC

resistor at the lowest temperature.

The two resistors (RT1 and RT2), allow the high-

temperature limit and low-temperature limit to be

programmed independently.

It should satisfy the 4 equations above. Refer to

Figure 9 for NTC function block.

NTC

LDO

RNTC

RT1

RT2

VT1

VT2

VT3

VT4

Figure 9. NTC Function Block

PCB Layout Guidelines

Efficient PCB layout is critical to meet specified

noise, efficiency, and stability requirements.

Refer to Figure 10 and the following design

considerations to improve circuit performance:

1) Route the power stage adjacent to their

grounds. Trace lengths in the high-current paths

and the current-sense resistor trace.

2) Keep the power ground away from all small

control signals, especially the feedback network.

3) Place the input capacitor as close as possible

to VDD and PGND.

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