NT5DS64M4AT NT5DS64M4AW

NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Preliminary

10/01

7

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (32Mb x 8)

1

DQS

CK, CK

DLL

RAS

CAS

CK

CS

WE

CK

Column-Address

Counter/Latch

Mode

10

A0-A12,

BA0, BA1

CKE

15

15

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

Bank1

Bank2

Bank3

13

9

1

2

2

8

8

8

Input

Register

1

1

1

1

1

16

16

2

16

clk

out

Data

Mask

Data

CK,

COL0

COL0

COL0

clk

in

DQS

Generator

8

8

8

8

8

16

DQ0-DQ7,

DM

DQS

1

Write

FIFO

&

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

512

(x16)

Registers

8192

13

CK