поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

HSP50214BVCZ датащи(PDF) 13 Page - Renesas Technology Corp

номер детали HSP50214BVCZ
подробное описание детали  Programmable Downconverter
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HSP50214BVCZ датащи(HTML) 13 Page - Renesas Technology Corp

Back Button HSP50214BVCZ Datasheet HTML 9Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 10Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 11Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 12Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 13Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 14Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 15Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 16Page - Renesas Technology Corp HSP50214BVCZ Datasheet HTML 17Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 62 page
background image
HSP50214B
FN4450 Rev 4.00
Page 13 of 62
May 1, 2007
Typically, the average input error is read from the Input Level
Detector port for use in AGC Applications. By setting the
threshold to 0, however, the average value of the input signal
can be read directly. The calculation is:
where “level” is the 24-bit value read from the 3 level
Detector Registers and “N” is the number of samples to be
integrated. Note that to get the RMS value of a sinusoid,
multiply the average value of the rectified sinusoid by 1.111.
For a full scale input sinusoid, this yields an RMS value of
approximately 3dBfS.
NOTE: 1.111 scales the rectified sinusoid average (2/
) to 1/2
.
In the HSP50214B, the polarity of the LSB’s of the
integration period pre-load is selectable. If Control Word 27,
Bit 23 is set to a logic one, the two LSB’s of the integration
period preload are set to logic ones. This allows a power of
two to be set for the integration period, for easy
normalization in the processor. If Control Word 27, Bit 23 is
set to a logic zero, then the two LSB’s of the integration
period preload are set to zeros as in the HSP50214.
Carrier Synthesizer/Mixer
The Carrier Synthesizer/Mixer Section of the HSP50214B is
shown in Figure 12. The NCO has a 32-bit phase
accumulator, a 10-bit phase offset adder, and a sine/cosine
ROM. The frequency of the NCO is the sum of a center
frequency Control Word, loaded via the microprocessor
interface (Control Word 3, Bits 0 to 31), and an offset
frequency, loaded serially via the COF and COFSYNC pins.
The offset frequency can be zeroed in Control Word 0, Bit 1.
Both frequency control terms are 32-bits and the addition is
modulo 232. The output frequency of the NCO is computed
as:
or in terms of the programmed value:
where N is the 32-bit sum of the center and offset frequency
terms, fC is the frequency of the carrier NCO sinusoids, fS is
the input sampling frequency, and INT is the integer of the
computation. See the Microprocessor Write Section on
instructions for writing Control Word 3.
For example, if N is 3267 (decimal), and fS is 65MHz, then fC
is 49.44Hz. If received data is modulated at a carrier
frequency of 10MHz, then the synthesizer/mixer should be
programmed for N = 27627627 (hex) or D89D89D8 (hex).
Because the input enable, ENI, controls the operation of the
phase accumulator, the NCO output frequency is computed
relative to the input sample rate, fS, not to fCLKIN. The
frequency control, N, is interpreted as two’s complement
because the output of the NCO is quadrature. Negative
frequency L.O.s select the upper sideband; positive frequency
L.O.s select the lower sideband. The range of the NCO is
-fS/2 to +fS/2. The frequency resolution of the NCO is fS/(232)
or approximately 0.015Hz when CLKIN is 65MSPS and ENI is
tied low.
dBFSRMS
20

1.111
 level

N
 16



log
=
(EQ. 2)
A) INPUT SIGNAL
C) THRESHOLD
B) RECTIFIED SIGNAL
D) ACCUMULATOR INPUTS
E) DETECTOR OUTPUT
F) CLOSED LOOP STEADY STATE
(CONSTANT INPUT)
FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR
fC
fS* N 2
32

,
=
(EQ. 3)
NINT fC 2
32 f
S

HEX ,
=
(EQ. 3A)
SHIFT REG
SYNC
REG
REG
COF
COFSYNC
SIN/COS
ROM
REG
REG
TO MIXERS
SIN
COS
CARRIER
FREQUENCY
†
CARRIER
FREQUENCY
CARRIER
32
32
10
18
18
MUX
0
COF
MUX
0
CLEAR
PHASE
ACCUMULATOR
CF
COF
ENABLE
†
R
E
G
REG
+
REG
+
† Controlled via microprocessor interface.
18
PHASE
OFFSET
†
PHASE
ACCUM
†
CARRIER
STROBE
†
CARRIER
LOAD ON
UPDATE
†
R
E
G
STROBE
†
PHASE
SYNC
CIRCUITRY
ENI
FIGURE 12. BLOCK DIAGRAM OF NCO SECTION
R
E
G
SYNCIN1
(fC)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com