HSP50214BVCZ datasheet(32/62 Pages) RENESAS

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HSP50214B

FN4450 Rev 4.00

Page 32 of 62

May 1, 2007

The Discriminator FIR filter input selections are made in

Control Word 27, Bits 18 and 19. The bit definitions are:

00 Item (1) described above.

01 Item (2) described above.

1X Item (3) described above.

Control Word 27, Bit 14 is used to control the Q input to the

coordinate converter. The bit definitions is:

I and Q enabled to the I/Q to R/Theta block.

The Q input to the I/Q to R/Theta block is zeroed.

The enable signals associated with the various input

selections to the Discriminator FIR filter are:

The data ready strobe from the coordinate con-

verter block.

The data ready strobe from the coordinate con-

verter block.

The enable signals associated with the various input

selections to the coordinate converter are:

The data ready signal to the coordinate converter

block when the resampler is bypassed. This is the

AGC output data ready signal.

The data ready to the coordinate converter block

when the resampler/halfband filters are enabled.

This is the resampler halfband filter block output

data ready signal.

The discriminator input is 18-bits, and the output is rounded

asymmetrically to 16-bits. The phase into the discriminator

can be multiplied by 20, 21, 22, or 23 (modulo 2

) to remove

PSK data modulation. All programmable parameters for the

Frequency Discriminator are set in Control Word 17. Bits 15

and 16 are the phase multiplier which represents the shift

applied to the input phase. For CW, the multiply should equal

20, (00). For BPSK, QPSK, and 8PSK, the multiply should

equal 21, (01); 22, (10); or 23, (11); respectively. Bit 14 is

used to enable or disable the discriminator. Bits 11-13 set the

decimation in the programmable FIR filter. Bit 10 sets the

filter symmetry type as either odd or even, bit 9 sets whether

the filter is asymmetric or symmetric, and bits 3-8 set the

number of FIR filter taps. Bits 0-2 set the number of delays in

the frequency discriminator.

Output Section

The Output Section routes the 7 types of processed signals to

output pins in three basic modes. These basic modes are:

Parallel Direct Output, Serial Direct Output, and the Buffer

RAM Output. The Serial and Parallel Direct Output modes

were designed to output data strobes and “real time”

continuous streams of data. The Buffer RAM Output mode

outputs data upon receipt of an asynchronous request from an

external DSP processor or other baseband processing

engine. The use of the interrupt signal from the

Programmable Down Converter in conjunction with the

request strobes from the controller ensures that data is

transferred only when both the controller and the

Programmable Down Converter are ready. The Buffer RAM

output can be operated in a First In First Out (FIFO) or

SNAPSHOT mode with the data output either via the 8-bit

processor interface or a 16-bit processor interface.

Parallel Direct Output Port Mode

The Parallel Direct Output Port Mode outputs two 16-bit words,

AOUT and BOUT, of “real time” data. Figure 30 details the

parallel output circuitry. Selection of the data source for the

AOUT and BOUT parallel outputs is done via Control Word 20,

Bits 22-23, and 20-21, respectively. The AOUT port can output

I, Magnitude, or Frequency data. The BOUT port can output Q,

Phase or Magnitude data. The upper bytes of AOUT and

BOUT are always in the parallel direct mode. The 16-bit parallel

direct mode is selected by setting Control Word 20, Bit 25, to

zero.

The DATARDY output is asserted during the first clock cycle

of the new data on the AOUT bus. The rate at which the data

out of the HSP50214 transitions and the rate at which

DATARDY is asserted can be different.

Data Transitions:

The transition rate of the parallel output data is dependent on

which of the three types of data is selected for the AOUT

Output channel: I (real symbols), |r| (magnitude), or f

(frequency). Q (quadrature symbols), ø (phase), or |r|

(magnitude) are available on the BOUT output. When selected

as an output, the I Q, |r|, and ø outputs transition at the symbol

rate. The f (frequency) output transitions at the discriminator

FIR filter output rate.

MAG

FREQ

PHAS

MAG

AOUT(15:8)

A(7:0)

RAM(15:8)

AOUT(7:0)

B(7:0)

BOUT(7:0)

RAM (7:0)

BOUT DIRECT PAR

AOUT DIRECT PAR

DATA SOURCE FOR LSB

†

BOUT(15:8)

B(15:8)

A(15:8)

RAM (15:0)

OUTPUT MODE

DATA SOURCE

†

OUTPUT MODE

DATA SOURCE

†

† Controlled via microprocessor interface.

FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM

DATARDY

(2’s COMPLEMENT)

(UNSIGNED BINARY)

(2’s COMPLEMENT)

(UNSIGNED BINARY)

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