9

LTC2604/LTC2614/LTC2624

2604f

BLOCK DIAGRA

SDO (Pin 10): Serial Interface Data Output. The serial

output of the shift register appears at the SDO pin. The data

transferred to the device via the SDI pin is delayed 32 SCK

rising edges before being output at the next falling edge.

This pin is used for daisy-chain operation.

2

15

1

GND

REF LO

REF A

REF B

CS/LD

SCK

REF D

REF C

SDO

SDI

2604 BD

16

3

4

14

DAC A

DAC D

5

7

6

8

10

12

9

13

DAC B

DAC C

DECODE

CONTROL

LOGIC

32-BIT SHIFT REGISTER

CLR

11

SDI

SDO

CS/LD

SCK

2604 F01

12

3

23

24

TI I G DIAGRA

Figure 1

CLR (Pin 11): Asynchronous Clear Input. A logic low at this

level-triggered input clears all registers and causes the

DAC voltage outputs to drop to 0V. CMOS and TTL-

compatible.