LTC1609 datasheet(13/40 Pages) LINER

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LTC2345-18

234518f

For more information www.linear.com/LTC2345-18

pin FuncTions

Pins that are the Same for All Digital I/O Modes

IN0+ to IN7+, IN0− to IN7− (Pins 1, 2, 3, 4, 5, 6, 7, 8, 9,

10, 11, 12, 13, 14, 47, and 48): Positive and Negative

Analog Inputs, Channels 0 to 7. The converter simultane-

ously samples and digitizes (VIN+ – VIN–) for all channels.

Wide input common mode range (0V ≤ VCM ≤ VDD) and

high common mode rejection allow the inputs to accept

a wide variety of signal swings. Full-scale input range is

determined by the channel’s SoftSpan configuration.

GND (Pins 15, 16, 17, 18, 20, 30, 41, 44, 45, 46, 49):

Ground. Solder all GND pins to a solid ground plane.

REFIN (Pin 19): Bandgap Reference Output/Reference

Buffer Input. An internal bandgap reference nominally

outputs 2.048V on this pin. An internal reference buffer

amplifies VREFIN to create the converter master reference

voltage VREFBUF = 2 • VREFIN on the REFBUF pin. When

using the internal reference, bypass REFIN to GND (Pin

20) close to the pin with a 0.1μF ceramic capacitor to filter

the bandgap output noise. If more accuracy is desired,

overdrive REFIN with an external reference in the range

of 1.25V to 2.2V.

REFBUF (Pin 21): Internal Reference Buffer Output. An

internal reference buffer amplifies VREFIN to create the

converter master reference voltage VREFBUF=2 • VREFINon

thispin,nominally4.096Vwhenusingtheinternalbandgap

reference. Bypass REFBUF to GND (Pin 20) close to the

pin with a 47μF ceramic capacitor. The internal reference

buffer may be disabled by grounding its input at REFIN.

With the buffer disabled, overdrive REFBUF with an ex-

ternal reference voltage in the range of 2.5V to 5V. When

using the internal reference buffer, limit the loading of any

external circuitry connected to REFBUF to less than 10µA.

Using a high input impedance amplifier to buffer VREFBUF

to any external circuits is recommended.

PD (Pin 22): Power Down Input. When this pin is brought

high, the LTC2345-18 is powered down and subsequent

conversion requests are ignored. If this occurs during a

conversion, the device powers down once the conversion

completes. If this pin is brought high twice without an

intervening conversion, an internal global reset is initi-

ated, equivalent to a power-on-reset event. Logic levels

are determined by OVDD.

LVDS/CMOS(Pin23):I/OModeSelect.TiethispintoOVDD

to select LVDS I/O mode, or to ground to select CMOS I/O

mode. Logic levels are determined by OVDD.

CNV (Pin 24): Conversion Start Input. A rising edge on

this pin puts the internal sample-and-holds into the hold

mode and initiates a new conversion. CNV is not gated

by CS, allowing conversions to be initiated independent

of the state of the serial I/O bus.

BUSY (Pin 38): Busy Output. The BUSY signal indicates

that a conversion is in progress. This pin transitions low-

to-high at the start of each conversion and stays high until

the conversion is complete. Logic levels are determined

by OVDD.

VDDLBYP(Pin40):Internal2.5VRegulatorBypassPin.The

voltage on this pin is generated via an internal regulator

operating off of VDD. This pin must be bypassed to GND

close to the pin with a 2.2μF ceramic capacitor. Do not

connect this pin to any external circuitry.

VDD (Pins 42, 43): 5V Power Supply. The range of VDD

is 4.75V to 5.25V. Connect Pins 42 and 43 together and

bypass the VDD network to GND with a shared 0.1μF

ceramic capacitor close to the pins.

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