LTC2271 datasheet(21/24 Pages) LINER

21 / 24 page

LTC2387-18

238718fa

For more information www.linear.com/LTC2387-18

the optional LVDS output DB± is enabled, and data is out-

put two bits at a time on DA± and DB±. Enabling the DB±

output increases the supply current from OVDD by about

3.6mA. In two-lane mode, five clock pulses are required

for CLK± (see Timing Diagrams).

Output Test Patterns

To allow in-circuit testing of the digital interface to the

ADC, there is a test mode that forces the ADC data outputs

to known values:

One-Lane Mode: 10 1000 0001 1111 1100

Two-Lane Mode: 11 0011 0000 1111 1100

The test pattern is enabled when the TESTPAT pin is

brought high.

BOARD LAYOUT

The LTC2387-18 requires a printed circuit board with a

clean unbroken ground plane. A multilayer board with an

internal ground plane in the first layer beneath the ADC is

recommended. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track

or underneath the ADC.

High quality ceramic bypass capacitors should be used

at the VDD, VDDL, OVDD, VCM, REFIN, and REFBUF pins.

Bypass capacitors must be located as close to the pins as

possible. Size 0402 ceramic capacitors are recommended

(except for REFBUF). The traces connecting the pins and

bypass capacitors must be kept short and should be made

as wide as possible.

Of particular importance is the capacitor between REFBUF

and REFGND, which should be a 10μF (X7R, 0805 size)

ceramic capacitor. This capacitor should be on the same

side of the circuit board as the ADC, and as close to the

device as possible. Adding a second, smaller capacitor in

parallel with the 10μF may degrade performance and is

not recommended.

Theanaloginputs,convertstart,anddigitaloutputsshould

not be routed next to each other. Ground fill and grounded

vias should be used as barriers to isolate these signals

from each other.

Exposed Package Pad

For good electrical and thermal performance, the exposed

pad on the bottom of the package must be soldered to a

large grounded pad on the PC board. This pad should be

connectedtotheinternalgroundplanesbyanarrayofvias.

Mechanical Stress Shift

The mechanical stress of mounting a part to a board can

cause subtle changes to the SNR and internal voltage

reference. The best soldering method is to use IR reflow

or convection soldering with a controlled temperature

profile. Hand soldering with a heat gun or a soldering iron

is not recommended.

applicaTions inForMaTion

LTC2271 датащи(PDF) 21 Page - Linear Technology

LTC2271 датащи(HTML) 21 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL