LTC2271 datasheet(20/24 Pages) LINER

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LTC2387-18

238718fa

For more information www.linear.com/LTC2387-18

Figure 12. Timing Diagram for a Single Conversion in One-Lane Mode

tCONV

238718 F12

CNV

D17

16 15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLK

DCO

MSB

LSB

applicaTions inForMaTion

Figure 13. Valid Time Window for Clocking Out Data

tFIRSTCLK

tLASTCLK

238718 F13

CNV

CLK

TIME WINDOW FOR CLOCKING OUT CONVERSION N

CONVERSION N

CONVERSION N+1

The LVDS signals should be routed on the PC board as

100Ω differential transmission lines and terminated at the

receiver with 100Ω resistors.

A conversion is started by the rising edge of CNV+. When

the conversion is complete, the most-significant data bit

is output on DA±. Data is then ready to be shifted out by

applying a burst of nine clock pulses to the CLK± input.

The data on DA± is updated by every edge of CLK±. An

echoed version of CLK± is output on DCO±. The edges of

DA± and DCO± are aligned, so DCO± can be used to latch

DA± in the FPGA. The timing of a single conversion is

shown in Figure 12.

Data must be clocked out after the current conversion is

complete,andbeforethenextconversionfinishes.Thevalid

time window for clocking out data is shown in Figure 13.

Note that it is allowed to be still clocking out data when

the next conversion begins.

Two-Lane Output Mode

At high sample rates the required LVDS interface data rate

can reach >400Mbps. Most FPGAs can support this, but

if a lower data rate is desired, the two-lane output mode

can be used. When the TWOLANES input pin is tied high,

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