LTC2602 datasheet(5/26 Pages) LINER

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LTC2321-16

232116fc

For more information www.linear.com/LTC2321-16

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground, or above VDD

or OVDD, they will be clamped by internal diodes. This product can handle

input currents up to 100mA below ground, or above VDD or OVDD, without

latch-up.

Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2 = 4.096V, fSMPL = 2MHz.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 0000 and 1111

1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or

+FS un-trimmed deviation from ideal first and last code transitions and

includes the effect of offset error.

Note 8: All specifications in dB are referred to a full-scale ±4.096V input

with REFIN = 4.096V.

Note 9: When REFOUT1,2 is overdriven, the internal reference buffer must

be turned off by setting REFINT = 0V.

Note 10: fSMPL = 2MHz, IREFBUF varies proportionally with sample rate.

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OVDD = 1.71V and

OVDD = 2.5V.

Note 13: tSCK of 15.6ns maximum allows a shift clock frequency up to

64MHz for rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: CNV is driven from a low jitter digital source, typically at OVDD

logic levels. This input pin has a TTL style input that will draw a small

amount of current.

Figure 1. Voltage Levels for Timing Specifications

0.8 • OVDD

0.2 • OVDD

50%

232116 F01

0.2 • OVDD

0.8 • OVDD

0.2 • OVDD

0.8 • OVDD

tDELAY

tWIDTH

tDELAY

aDc TiMing characTerisTics

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSMPL

Maximum Sampling Frequency

Msps

tCYC

Time Between Conversions

(Note 11) tCYC = tCNVH + tCONV + tREADOUT

500

1000000

tCONV

Conversion Time

220

tCNVH

CNV High Time

tDSCKHCNVH

SCK Delay Time to CNV↑

(Note 11)

tSCK

SCK Period

(Notes 12, 13)

15.6

tSCKH

SCK High Time

tSCKL

SCK Low Time

tDSCKCLKOUT

SCK to CLKOUT Delay

(Note 12)

2.8

tDCLKOUTSDOV

SDO Data Valid Delay from CLKOUT↓ CL = 5pF (Note 12)

tHSDO

SDO Data Remains Valid Delay from

CLKOUT↓

CL = 5pF (Note 11)

tDCNVSDOV

SDO Data Valid Delay from CNV↓

CL = 5pF (Note 11)

2.5

tDCNVSDOZ

Bus Relinquish Time After CNV↑

(Note 11)

tWAKE

REFOUT1,2 Wakeup Time

CREFOUT1,2 = 10μF

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C (Note 4).

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