LTC2221 datasheet(23/32 Pages) LINER

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LTC2220/LTC2221

22201fa

duty cycle stabilizer will maintain a constant 50% internal

duty cycle. If the clock is turned off for a long period of

time, the duty cycle stabilizer circuit will require one

hundred clock cycles for the PLL to lock onto the input

clock. To use the clock duty cycle stabilizer, the MODE pin

should be connected to 1/3VDD or 2/3VDD using external

resistors.

The lower limit of the LTC2220/LTC2221 sample rate is

determined by droop of the sample-and-hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The specified minimum operat-

ing frequency for the LTC2220/LTC2221 is 1Msps.

Digital Output Modes

The LTC2220/LTC2221 can operate in several digital out-

put modes: LVDS, CMOS running at full speed, and CMOS

demultiplexed onto two buses, each of which runs at half

speed. In the demultiplexed CMOS modes the two buses

(referred to as bus A and bus B) can either be updated on

alternate clock cycles (interleaved mode) or simultaneously

(simultaneous mode). For details on the clock timing, refer

to the timing diagrams.

The LVDS pin selects which digital output mode the part

uses. This pin has a four-level logic input which should be

connected to GND, 1/3VDD, 2/3VDD or VDD. An external

resistor divider can be used to set the 1/3VDD or 2/3VDD

logic values. Table 2 shows the logic states for the LVDS

pin.

APPLICATIO S I FOR ATIO

LTC2220/LTC2221

22201 F13a

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 13a. Digital Output Buffer in CMOS Mode

DIGITAL OUTPUTS

Table 1. Output Codes vs Input Voltage

AIN

+ – AIN–

D11 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

1111 1111 1111

0111 1111 1111

+0.999512V

1111 1111 1111

0111 1111 1111

+0.999024V

1111 1111 1110

0111 1111 1110

+0.000488V

1000 0000 0001

0000 0000 0001

0.000000V

1000 0000 0000

0000 0000 0000

–0.000488V

0111 1111 1111

1111 1111 1111

–0.000976V

0111 1111 1110

1111 1111 1110

–0.999512V

0000 0000 0001

1000 0000 0001

–1.000000V

0000 0000 0000

1000 0000 0000

<–1.000000V

0000 0000 0000

1000 0000 0000

22201 F12Ía

ENC–

1.6V

VTHRESHOLD = 1.6V

ENC+

0.1

µF

LTC2220/

LTC2221

22201 F12b

ENC–

ENC+

130

Ω

3.3V

130

Ω

MC100LVELT22

LTC2220/

LTC2221

Ω

Figure 12a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 12b. ENC Drive Using a CMOS to PECL Translator

Table 2. LVDS Pin Function

LVDS

Digital Output Mode

GND

Full-Rate CMOS

1/3VDD

Demultiplexed CMOS, Simultaneous Update

2/3VDD

Demultiplexed CMOS, Interleaved Update

VDD

LVDS

Digital Output Buffers (CMOS Modes)

Figure 13a shows an equivalent circuit for a single output

buffer in the CMOS output mode. Each buffer is powered

by OVDD and OGND, which are isolated from the ADC

power and ground. The additional N-channel transistor in

the output driver allows operation down to voltages as low

as 0.5V. The internal resistor in series with the output

makes the output appear as 50

Ω to external circuitry and

may eliminate the need for external damping resistors.

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