LTC2221 datasheet(12/32 Pages) LINER

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LTC2220/LTC2221

22201fa

(CMOS Mode)

AIN+ (Pins 1, 2): Positive Differential Analog Input.

AIN– (Pins 3, 4): Negative Differential Analog Input.

REFHA (Pins 5, 6): ADC High Reference. Bypass to

Pins 7, 8 with 0.1

µF ceramic chip capacitor, to Pins 11, 12

with a 2.2

µF ceramic capacitor and to ground with 1µF

ceramic capacitor.

REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,

6 with 0.1

µF ceramic chip capacitor. Do not connect to

Pins 11, 12.

REFHB (Pins 9, 10): ADC High Reference. Bypass to

Pins 11, 12 with 0.1

µF ceramic chip capacitor. Do not

connect to Pins 5, 6.

REFLA (Pins 11, 12): ADC Low Reference. Bypass to

Pins 9, 10 with 0.1

µF ceramic chip capacitor, to Pins 5, 6

with a 2.2

µF ceramic capacitor and to ground with 1µF

ceramic capacitor.

VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to

GND with 0.1

µF ceramic chip capacitors.

GND (Pins 16, 61, 64): ADC Power Ground.

ENC+ (Pin 17): Encode Input. Conversion starts on the

positive edge.

ENC– (Pin 18): Encode Complement Input. Conversion

starts on the negative edge. Bypass to ground with 0.1

µF

ceramic for single-ended ENCODE signal.

SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-

ing SHDN to GND and OE to GND results in normal

operation with the outputs enabled. Connecting SHDN to

GND and OE to VDD results in normal operation with the

outputs at high impedance. Connecting SHDN to VDD and

OE to GND results in nap mode with the outputs at high

impedance. Connecting SHDN to VDD and OE to VDD

results in sleep mode with the outputs at high impedance.

OE (Pin 20): Output Enable Pin. Refer to SHDN pin

function.

PI FU CTIO S

DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32,

35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high

impedance in full rate CMOS mode.

OGND (Pins 25, 33, 41, 50): Output Driver Ground.

OVDD (Pins 26, 34, 42, 49): Positive Supply for the

Output Drivers. Bypass to ground with 0.1

µF ceramic chip

capacitor.

OFB (Pin 37): Over/Under Flow Output for B Bus. High

when an over or under flow has occurred. At high imped-

ance in full rate CMOS mode.

CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux

mode with interleaved update, latch B bus data on the

falling edge of CLKOUTB. In demux mode with simulta-

neous update, latch B bus data on the rising edge of

CLKOUTB. This pin does not become high impedance in

full rate CMOS mode.

CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A

bus data on the falling edge of CLKOUTA.

DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,

54, 55): Digital Outputs, A Bus. DA11 is the MSB.

OFA (Pin 56): Over/Under Flow Output for A Bus. High

when an over or under flow has occurred.

LVDS (Pin 57): Output Mode Selection Pin. Connecting

LVDS to 0V selects full rate CMOS mode. Connecting

LVDS to 1/3VDD selects demux CMOS mode with simulta-

neous update. Connecting LVDS to 2/3VDD selects demux

CMOS mode with interleaved update. Connecting LVDS to

VDD selects LVDS mode.

MODE (Pin 58): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and turns the clock duty cycle

stabilizer off. Connecting MODE to 1/3VDD selects offset

binary output format and turns the clock duty cycle stabi-

lizer on. Connecting MODE to 2/3VDD selects 2’s comple-

ment output format and turns the clock duty cycle stabi-

lizer on. Connecting MODE to VDD selects 2’s complement

output format and turns the clock duty cycle stabilizer off.

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