LTM4606 datasheet(17/24 Pages) LINER

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LTM8050

8050fc

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Figure 4. In Negative Output Voltage Applications, Prevent Adverse Effects from Fast Rising VIN by Adding Clamp and Rectifying Diodes

APPLICATIONS INFORMATION

Negative Output Considerations

The LTM8050 may be configured to generate a negative

output voltage. Examples of this are shown in the Typical

Applications section. For very fast rising input voltages,

care must be taken to ensure that start-up does not cre-

ate excessive surge currents that may create unwanted

voltages or even damage the LTM8050.

Consider the circuit in Figure 4. If a step input is applied

between VIN and system GND, the CIN and COUT capaci-

tors form an AC divider network that tends to create a

positive voltage on system VOUT. In order to protect the

load from seeing an excessive inverted voltage, an anti-

parallel Schottky diode may be used to clamp the voltage.

Furthermore, current flowing out of the BIAS pin can have

adverse affects. To prevent this from happening, apply a

series resistor (about 200Ω) and Schottky diode between

BIAS and its voltage source.

Thermal Considerations

The LTM8050 output current may need to be derated if

it is required to operate in a high ambient temperature or

deliver a large amount of continuous power. The amount

of current derating is dependent upon the input voltage,

output power and ambient temperature. The temperature

rise curves given in the Typical Performance Character-

istics section can be used as a guide. These curves were

generated by a LTM8050 mounted to a 40cm2 4-layer FR4

printed circuit board. Boards of other sizes and layer count

can exhibit different thermal behavior, so it is incumbent

upon the user to verify proper operation over the intended

system’sline,loadandenvironmentaloperatingconditions.

The thermal resistance numbers listed in Page 2 of the

data sheet are based on modeling the µModule package

mounted on a test board specified per JESD51-9 (Test

Boards for Area Array Surface Mount Package Thermal

Measurements). The thermal coefficients provided in this

page are based on JESD 51-12 (Guidelines for Reporting

and Using Electronic Package Thermal Information).

Forincreasedaccuracyandfidelitytotheactualapplication,

many designers use FEA to predict thermal performance.

To that end, Page 2 of the data sheet typically gives four

thermal coefficients:

θJA – Thermal resistance from junction to ambient

θJCbottom – Thermal resistance from junction to the

bottom of the product case

θJCtop – Thermal resistance from junction to top of the

product case

θJB – Thermal resistance from junction to the printed

circuit board

While the meaning of each of these coefficients may seem

to be intuitive, JEDEC has defined each to avoid confusion

and inconsistency. These definitions are given in JESD

51-12, and are quoted or paraphrased below:

θJA is the natural convection junction-to-ambient air

thermal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred to as

VIN

RUN/SS

ADJ

VOUT

GND

8050 F04

LTM8050

VIN

VOUT (NEGATIVE VOLTAGE)

ADD AN ANTI-PARALLEL

DIODE TO CLAMP POSITIVE

VOLTAGE SPIKE

ADD A SERIES RESISTOR AND

DIODE TO PREVENT CURRENT

FROM FLOWING OUT OF BIAS

INRUSH

CURRENT

CAN CAUSE

A POSITIVE

TRANSIENT

ON VOUT

CIN

COUT

PGOOD

SYNC

AUX

BIAS

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