LTM8049 datasheet(20/32 Pages) LINER

20 / 32 page

LTM4653

Rev 0

For more information www.analog.com

4. θJB, the thermal resistance from junction to the printed

circuit board, is the junction-to-board thermal resis-

tance where almost all of the heat flows through the

bottom of the µModule regulator and into the board,

and is really the sum of the θJCbottom and the thermal

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from the

package, using a two sided, two layer board. This board

is described in JESD51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 7; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4653, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complicationwithoutsacrificingmodelingsimplicity—but

alsonotignoringpracticalrealities—anapproachhasbeen

taken using FEA software modeling along with laboratory

testing in a controlled-environment chamber to reason-

ably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4653 and the specified PCB with all of the correct

material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

definedJEDECenvironmentconsistentwithJESD51-9and

JESD51-12topredictpowerlossheatflowandtemperature

readings at different interfaces that enable the calculation

of the JEDEC-defined thermal resistance values; (3) the

model and FEA software is used to evaluate the LTM4653

with heat sink and airflow; (4) having solved for and

analyzed these thermal resistance values and simulated

various operating conditions in the software model, a

thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled envi-

ronment chamber while operating the device at the same

power loss as that which was simulated. The outcome of

this process and due diligence yields the set of derating

APPLICATIONS INFORMATION

4653 F07

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Figure 7. Graphical Representaion of JESD51-12 Thermal Coefficients

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