LTC6902 datasheet(16/28 Pages) LINER

16 / 28 page

LTM4632

4632fc

For more information www.linear.com/LTM4632

The Pin Configuration section typically gives four thermal

coefficients explicitly defined in JESD 51-12; these coef-

ficients are quoted or paraphrased below:

1. θJA, the thermal resistance from junction to ambient,

is the natural convection junction-to-ambient air ther-

mal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred to

as “still air” although natural convection causes the

air to move. This value is determined with the part

mounted to a JESD 51-9 defined test board, which

does not reflect an actual application or viable operat-

ing condition.

2. θJCbottom, the thermal resistance from junction to

ambient, is the natural convection junction-to-ambi-

ent air thermal resistance measured in a one cubic

foot sealed enclosure. This environment is sometimes

referred to as “still air” although natural convection

causes the air to move. This value is determined with

the part mounted to a JESD 51-9 defined test board,

which does not reflect an actual application or viable

operating condition.

3. θJCtop, the thermal resistance from junction to top of

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θJCbottom, this value may be useful

for comparing packages but the test conditions don’t

generally match the user’s application.

4. θJB, the thermal resistance from junction to the

printed circuit board, is the junction-to-board thermal

resistance where almost all of the heat flows through

the bottom of the µModule and into the board, and

is really the sum of the θJCbottom and the thermal

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from

the package, using a two sided, two layer board. This

board is described in JESD 51-9.

APPLICATIONS INFORMATION

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 8; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a μModule. For example, in nor-

mal board-mounted applications, never does 100% of

the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package as the standard defines for

θJCtop and θJCbottom, respectively. In practice, power loss

is thermally dissipated in both directions away from the

package–granted, in the absence of a heat sink and air-

flow, a majority of the heat flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are

not exactly linear with respect to total package power loss.

To reconcile this complication without sacrificing model-

ing simplicity–but also, not ignoring practical realities–an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-12 to predict power loss heat flow and tempera-

ture readings at different interfaces that enable the cal-

culation of the JEDEC-defined thermal resistance values;

(3) the model and FEA software is used to evaluate the

µModule with heat sink and airflow; (4) having solved for

and analyzed these thermal resistance values and simu-

lated various operating conditions in the software model,

a thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled-envi-

ronment chamber while operating the device at the same

LTC6902 датащи(PDF) 16 Page - Linear Technology

LTC6902 датащи(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL