LTM4630 datasheet(20/34 Pages) LINER

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LTM4630

4630fa

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APPLICATIONS INFORMATION

θJB, the thermal resistance from junction to the printed

circuitboard,isthejunction-to-boardthermalresistance

where almost all of the heat flows through the bottom of

the µModule and into the board, and is really the sum of

the

θJCbottom and the thermal resistance of the bottom

of the part through the solder joints and through a por-

tion of the board. The board temperature is measured a

specified distance from the package, using a two sided,

two layer board. This board is described in JESD 51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule. For example, in normal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sively through the top or exclusively through bottom of the

µModule—asthestandarddefinesfor

θJCtopandθJCbottom,

respectively.Inpractice,powerlossisthermallydissipated

in both directions away from the package—granted, in the

absence of a heat sink and airflow, a majority of the heat

flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JSED51-9 to predict power loss heat flow and temperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-definedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamberwhileoperatingthedeviceatthesamepowerloss

as that which was simulated. An outcome of this process

and due-diligence yields a set of derating curves provided

in other sections of this data sheet. After these laboratory

test have been performed and correlated to the µModule

model, then the

θJB and θBA are summed together to cor-

relate quite well with the µModule model with no airflow or

heat sinking in a properly define chamber. This

θJB + θBA

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

4630 F10

µMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

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