LTC7130 datasheet(13/36 Pages) LINER

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LTC7130

7130fb

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Frequency Selection and Phase-Locked Loop

(FREQ and MODE/PLLIN Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

If the MODE/PLLIN pin is not being driven by an external

clock source, the FREQ pin can be used to program the

controller’s operating frequency from 250kHz to 770kHz.

There is a precision 10µA current flowing out of the FREQ

pin so that the user can program the controller’s switch-

ing frequency with a single resistor to SGND. A curve

is provided later in the Applications Information section

showing the relationship between the voltage on the FREQ

pin and switching frequency.

A phase-locked loop (PLL) is available on the LTC7130

to synchronize the internal oscillator to an external clock

source that is connected to the MODE/PLLIN pin. The PLL

loop filter network is integrated inside the LTC7130. The

phase-locked loop is capable of locking any frequency

withintherangeof250kHzto770kHz.Thefrequencysetting

resistor should always be present to set the controller’s

initial switching frequency before locking to the external

clock. The controller operates in forced continuous mode

when it is synchronized.

Sensing the Output Voltage with a

Differential Amplifier

The LTC7130 includes a low offset, high input impedance,

unity-gain, high bandwidth differential amplifier for ap-

plications that require true remote sensing. Sensing the

load across the load capacitors directly greatly benefits

regulation in high current, low voltage applications, where

board interconnection losses can be a significant portion

of the total error budget. Connect DIFFP to the output load,

and DIFFN to the load ground. See Figure 1.

TheLTC7130differentialamplifierhasatypicaloutputslew

rate of 2V/µs. The amplifier is configured for unity gain,

meaning that the difference between DIFFP and DIFFN is

translated to DIFFOUT, relative to SGND.

OPERATION

Figure 1. Differential Amplifier Connection

DIFFOUT

LTC7130

DIFFP

COUT

VOUT

DIFFN

VFB

7130 F01

–

DIFFAMP

Care should be taken to route the DIFFP and DIFFN PCB

traces parallel to each other all the way to the remote

sensing points on the board. In addition, avoid routing

these sensitive traces near any high speed switching

nodes in the circuit. Ideally, the DIFFP and DIFFN traces

should be shielded by a low impedance ground plane to

maintain signal integrity. The maximum output voltage is

limited to 3.5V when using the differential amplifier. If the

differential amplifier is not used, tie the feedback divider

directlyacrosstheoutputwithitscenterpointconnectedto

VFB and ground the SNSD+ pin. In this case the maximum

supported VOUT is 5V.

Power Good (PGOOD Pin)

The PGOOD pin is connected to the open drain of an

internal N-channel MOSFET. The MOSFET turns on and

pulls the PGOOD pin low when the VFB pin voltage is not

within ±10% of the 0.6V reference voltage. The PGOOD

pin is also pulled low when the RUN pin is below 1.1V or

when the LTC7130 is in the soft-start or tracking up phase.

When the VFB pin voltage is within the ±10% regulation

window, the MOSFET is turned off and the pin is allowed

to be pulled up by an external resistor to a source of up

to 6V. The PGOOD pin will flag power good immediately

whentheVFBpiniswithintheregulationwindow.However,

there is an internal 20µs power-bad mask when the VFB

goes out of the window.

Inductor DCR Sensing Temperature Compensation

(ITEMP Pin)

Inductor DCR current sensing provides a lossless method

of sensing the instantaneous current. Therefore, it can

provide higher efficiency for applications with high output

currents. However, the DCR of a copper inductor typically

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