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LT8601

8601fa

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applicaTions inForMaTion

Thermal Considerations

Care should be taken in the layout of the PCB to ensure

good heat sinking of the LT8601. The exposed pad on

the bottom of the package must be soldered to a ground

plane. This ground should be tied to large copper layers

below with thermal vias; these layers will spread heat

dissipated by the LT8601. Recommended layer use for

a 4-layer board is:

Layer 1 (Components): use 2oz copper; unbroken high

frequency/high current routing (CIN loop, SW node, BST

node, inductor, COUT), high current DC routing, ground

plane on remainder

Layer 2 (Internal): Unbroken ground plane

Layer 3 (Internal): Signal routing, ground plane on

remainder

Layer 4 (Bottom): Use 2oz copper; high current DC rout-

ing (VIN, VOUT), ground plane on remainder

Placing additional vias can reduce thermal resistance fur-

ther. Many small thermal vias are better than a few large

ones. Following these PCB design guidelines can reduce

θJA to 22°C/W.

Power dissipation within the LT8601 can be estimated by

adding the power dissipated in each channel. Calculate

each channel’s power loss from an efficiency measure-

ment and subtract the inductor loss. The die temperature

is calculated by multiplying the total LT8601 power dissi-

pation by the thermal resistance from junction to ambient

θJA, and adding the ambient temperature. The maximum

load current should be derated as the die temperature

approaches the maximum junction rating. The LT8601 will

stop switching if the internal temperature rises too high.

This thermal protection is above the maximum operating

temperature and is intended as a failsafe only.

Even with the best thermal practices, the LT8601 must be

derated at high ambient temperature. The thermal derat-

ing curves in Figure 9 show the front page application

(Ch1: 5V, Ch2: 3.3V, Ch3: 1.8V). The PCB layout is as

described above and the θJA is 22°C/W. The output cur-

rents are decreased uniformly as a percentage of maxi-

mum. Although derating is application dependent, this set

of curves is representative of typical applications with a

range of frequencies and input voltages.

Figure 9. Thermal Derating, E- and I-Grade

3.5in x 3.5in 4–LAYER BOARD

2oz Cu TOP AND BOTTOM

LIMITED BY MAXIMUM

JUNCTION TEMPERATURE

θJA = 22°C/W

12VIN, 1MHz

12VIN, 2.2MHz

24VIN, 1MHz

24VIN, 2.2MHz

AMBIENT TEMPERATURE (°C)

100

125

100

Figure 10. Thermal Derating, E and I–Grade

8601 F09

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