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LT8601

8601fa

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Figure 6. Power-On Reset Timing

applicaTions inForMaTion

used, set RT to the center of the range. For example, if

the synchronization signal will be 400kHz to 600kHz, the

RT should be selected for 500kHz.

For some applications it is desirable for the LT8601 to

operate in pulse-skipping mode, offering two major differ-

ences from Burst Mode operation. First, in pulse-skipping

mode the clock stays awake at all times and all switching

cycles are aligned to the clock. Second, full frequency

switching is reached at a lower output load in pulse-skip-

ping than Burst Mode operation. These two differences

come at the expense of increased quiescent current for

pulse-skipping. To enable pulse-skipping mode, the SYNC

pin is tied high either to a logic output or to the INTVCC

pin.

Do not leave the SYNC pin floating.

Power Good Comparators

Each channel of the LT8601 has a power good compara-

tor that monitors their corresponding feedback voltage

when the LT8601 is enabled. The threshold of power good

comparator is 0.92V to 1.08V for the high voltage chan-

nels, and 736mV to 864mV for the low voltage channel.

The PG outputs are open-drain and have a recommended

external pull-up resistance value of 20k or less. An appro-

priate pull-up resistance value will take into consideration

the specific application configuration and the leakage cur-

rent of the PG pin.

Power-On Reset Timer

The power-on reset timer circuit provides a programma-

ble reset timer. The POREN pin is the enable for the reset

timer and includes a 1μA (typical) internal pull-up. Once

enabled, the reset timer begins an internal clock counter

that terminates after 64 cycles. Upon counter termination,

the RST open-drain output releases allowing the pin to

transition high. The RST output includes a weak, 100kΩ,

internal pull-up resistor to approximately 2V.

The power-on reset timeout period, tRST, can be pro-

grammed by connecting a capacitor, CPOR, between the

CPOR pin and ground. The value of tRST is calculated by:

tRST = 35.2 • CPOR

Figure 7. Sequencing the Outputs and POR

8601 F07

START

INTVCC

POREN

TRKSS1

PG3

LT8601

INTVCC

RUN3

PG2

TRKSS2

PG1

RST

where CPOR is in pF and tRST is in microseconds. For

example, using a capacitor value of 8.2nF gives a 289ms

reset timeout period. The accuracy of tRST will be deter-

mined by several factors including the accuracy and

temperature coefficient of the capacitor CPOR, parasitic

capacitance on the CPOR pin and board trace, and sys-

tem noise. It is not recommended to use capacitor values

greater than 10nF for best accuracy. Figure 6 shows the

power-on reset timing.

Sequencing

The LT8601 provides great flexibility in sequencing the

3 channels and the power-on reset timer. Each channel

has a power good output (PG1 to PG3) and a control-

ling input (TRKSS1, TRKSS2 and RUN3). The POR has

a control input (POREN) and a reset output (RST). All

4 outputs (PG1-PG3, RST) are open-drain, and all 4 inputs

(TRKSS1/2, RUN3, POREN) have internal pull-up currents

to reduce external component counts when not driven by

a PG pin. The soft-start function on the TRKSS pins will

1ms/DIV

POREN

1V/DIV

CPOR

1V/DIV

RST

2V/DIV

8601 F06

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