1

dc2226Afa

DEMO MANUAL DC2226A

DESCRIPTION

LTC6951

Multichannel JESD204B ADC

with Clocking

Demonstration Circuit 2226A-A is a reference design

for a four-channel, 250Msps ADC system consist-

ing of two LTC®2123, dual 14-bit 250Msps ADCs and

a JESD204B Subclass 1 clocking solution based on

the LTC6951 Clock Synthesizer with Integrated VCO.

Other dash options reserved for future use. No external

clock source is required to operate the board; however,

the onboard 100MHz reference oscillator may be by-

passed, allowing synchronization to other equipment.

L

, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ParallelSync and PScope are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

Figure 1 is a block diagram of the DC2226A clock con-

figuration, consisting of two LTC6951s in a JESD204B

subclass 1, ParallelSync™ configuration. More detailed

information is available on the LTC6951 product page.

Design files for this circuit board are available at

http://www.linear.com/demo/DC2226A

/1

/1

/1

10k

BB

LTC6951#2

U10

CP

TUNE

125MHz, FPGA CLOCK

15.625MHz, ADC2 SYSREF

2GHz, MUTED

250MHz, ADC2 CLOCK

PWRDN

1nF

56.2

56.2

BVCO

1µF

CMA

CMB

CMC

TB

1µF

100

SYNC

1µF

1µF

470nF

1.5nF

68nF

10

5V

3.3V

BB

LTC6951#1

U13

CP

TUNE

15.625MHz, FPGA SYSREF

15.625MHz, ADC1 SYSREF

2GHz, MUTED

250MHz, ADC1 CLOCK

PWRDN

DC2226 F01

1nF

56.2

56.2

BVCO

1µF

CMA

CMB

CMC

TB

1µF

100

SYNC

1µF

1µF

470nF

1.5nF

68nF

10

5V

3.3V

CK

D

SYNC

PULSE

LTC6951

REF INPUT

LTC6951

SYNC PULSE

SYNC TO REF TIMING

SYNC HELD HIGH A

MINIMUM OF 1ms

LTC6954-4

REFERENCE DISTRIBUTION

OUT0SEL

OUT1SEL

OUT2SEL

1µF

100MHz

REFERENCE

50

1µF

Q

CK

D

Q

1µF

10k

10k

Figure 1. Subclass 1 ParallelSync Design Example