K4M51163LE - Y(P)C/L/F

February 2004

Mobile-SDRAM

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next

higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

Parameter

Symbol

Version

Unit

Note

-80

-1H

-1L

Row active to row active delay

16

19

19

ns

1

RAS to CAS delay

19

19

24

ns

1

Row precharge time

19

19

24

ns

1

Row active time

48

50

60

ns

1

100

us

Row cycle time

67

69

84

ns

1

Last data in to row precharge

2

CLK

2

Last data in to Active delay

tRDL + tRP

-

3

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

4

Number of valid output data

CAS latency=3

2

ea

5

Number of valid output data

CAS latency=2

1

Number of valid output data

CAS latency=1

0