MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE

MP2930 Rev. 1.01

www.MonolithicPower.com

13

10/30/2013

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to generate a negative offset. The voltage

of OFS. The negative offset is:

OFS

R

REF

R

0.4

OFFSET

V





(10)

The maximum Negative Offset for MP2930 is

150mV.

Enable and Disable

While in shutdown mode, the PWM outputs are

held in a Hi-Z state, and the SD signal is pulled

low to assure the Intelli-phase remain off. The

following input conditions must be met to start

MP2932.

1. VCC must reach the internal power-on reset

(POR) rising threshold.

2.

EN_PWR is used to coordinate the power

sequencing

between

VCC

and

another

voltage rail. The enable comparator holds

the MP2932 in shutdown until the voltage at

EN_PWR rises above 0.875V.

3. The voltage on EN_VTT must be higher than

0.875V to enable the controller. This pin is

typically connected to the output of VTT VR.

10k

Ω

910

Ω

MP2930 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

EN_PWR

ENABLE

COMPARATOR

0.875V

0.875V

EN_VTT

POR

CIRCUIT

+12V

SOFT-START

AND

FAULT LOGIC

Figure 6

—Power Sequencing Using

Threshold Sensitive Enable (EN) Function

When all conditions are satisfied, MP2930

begins the soft-start and ramps the output

voltage to 1.1V first. After remaining at 1.1V for

some time, MP2930 reads the ID code at ID

input pins. If the ID code is valid, MP2930 will

regulate the output to the final ID setting. If the

ID code is OFF code, MP2930 will shutdown,

and cycling VCC, EN_PWR or EN_VTT is

needed to restart.

Soft-Start

MP2930 based VR has 4 periods during soft-

start as shown in Figure 7. After VCC, EN_VTT

and

EN_PWR

reach

their

POR/enable

thresholds, the controller will have fixed delay

begin first soft-start ramp until the output

voltage

reaches

1.1V

voltage.

Then,

the

controller will regulate the VR voltage at 1.1V

period, MP2930 reads the ID signals. If the ID

code is valid, MP2930 will initiate the second

soft-start ramp until the voltage reaches the ID

voltage minus offset voltage.

500us/DIV

EN_VTT

VR_RDY

1.1V

Figure 7

—Soft-Start Waveforms

The soft-start time is the sum of the 4 periods,

as shown in Equation (12):

d4

t

d3

t

d2

t

d1

t

SS

t









(12)

the time to obtain valid ID voltage. If the ID is

valid before the output reaches the 1.1V, the

minimum time to validate the ID input is 500ns.

DAC voltage change at 6.25mV per step. The

time for each step is determined by the

frequency of the soft-start oscillator which is