MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE

MP2930 Rev. 1.01

www.MonolithicPower.com

12

10/30/2013

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compared to sawtooth waveforms to generate

the PWM signals. The PWM signals control the

timing of the MP86961 and regulate the

converter output to the specified reference

voltage. The internal and external circuitry,

which control voltage regulation are shown in

Figure 4.

The

MP2930

incorporates

an

internal

differential

remote-sense

amplifier

in

the

feedback path, which results in a more accurate

means of sensing output voltage. Connect the

microprocessor sense pins to the non-inverting

input (VSEN) and inverting input (RGND) of the

remote-sense

amplifier.

The

remote-sense

output (VDIFF) is connected to the inverting

input of the error amplifier through an external

resistor.

Each ID input offers a 45µA pull-up to an

internal 2.5V source for use with open-drain

outputs. The pull-up current diminishes to zero

above the logic threshold to protect voltage-

sensitive

output

devices.

External

pull-up

resistors can augment the pull-up current

sources if case leakage into the driving device

is greater than 45µA.

Load-Line Regulation

As the load current increases from zero, the

output voltage will drop from the ID table value

by an amount proportional to load current to

achieve the load-line.

Adding a Droop can help to reduce the output

voltage spike that result from fast load-current

demand changes.

As shown in Figure 4, a current proportional to

flows from FB through a load-line regulation

proportional to the output current. It can be

derived from Equation (6):

FB

R

AVG

I

DROOP

V



(6)

The regulated output voltage is reduced by the

function

a

load

current,

it’s derived by

combining Equation (6) with the appropriate

sensing current expression defined by the

current sense method employed in Equation (7).























FB

R

ISEN

R

X

R

N

OUT

I

OFS

V

REF

V

OUT

V

(7)

sense resistor connected to the ISEN+ pin, and

depending on the sensing method.

Therefore the equivalent load-line impedance

(Droop

impedance),

can

be

derived

from

Equation (8):

ISEN

R

X

R

N

FB

R

LL

R



(8)

Output Voltage Offset Programming

In Figure 5, OFS pin is used to generate no-

load offset. A resistor RREF between DAC and

equal to the desired offset voltage.

R

C

FB

DAC

VCC

OR

GND

R

REF

OFS

GND

VCC

1.6V

0.4V

DYNAMIC

ID D/A

E/A

MP2930

REF

REF

OFS

Figure 5

—Output Voltage Offset

Programming

to generate a positive offset. The voltage

across it is regulated to 1.6V. This causes a

positive offset is:

OFS

R

REF

R

1.6

OFFSET

V





(9)