MP023 – PRIMARY-SIDE CC/CV CONTROLLER

MP023 Rev. 1.1

www.MonolithicPower.com

19

7/18/2016

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SM

S_ ON

PK

FBS _ Max

FB_ SD

PO

D

NL

TI

t

t

N(V

V )









(15)

Combine Equation (15) and the relationship of

maximum switching frequency.

PCB Layout Guidelines

Efficient PCB layout is critical for stable

operation, good EMI, and good thermal

performance. For best results, refer to Figure

16 and follow the guidelines below.

1. Minimize the loop area formed by the input

capacitor, the primary transformer winding,

the MOSFET drain source, and the sensing

resistor to reduce EMI noise.

2. Minimize the voltage jumping area, such as

the MOSFET drain, the anode of the

secondary diode, etc. for better EMI.

3. Minimize the clamp circuit loop to reduce

EMI.

4. Minimize the secondary loop area of the

output diode and output filter to reduce EMI

noise. Sufficient copper areas should be

provided at the cathode terminal of the

output diode to act as a heat sink.

5. Place the AC input away from the switching

nodes to minimize any noise coupling that

may bypass the input filter.

6. Place the bypass capacitor as close to the

IC as possible.

7. Place the feedback resistors next to FB and

minimize the feedback sampling loop to

minimize noise coupling.

8. Use a single-point connection at the

negative terminal of the input filter capacitor

for the IC GND and bias winding return.

Top Layer

Bottom Layer

Figure 16: Recommended Layout

Design Example

Table 3 is a design example following the

application guidelines.

Table 3: Design Example

85Vac~265Vac

47Hz/63Hz

5V

2.4A

70kHz

Figure 17 shows the detailed application

schematic. For more device applications,

please refer to the related evaluation board

datasheets.