MP8765 ─ 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

MP8765 Rev. 1.01

www.MonolithicPower.com

14

2/10/2015

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up

down

IN START

down

(R

R

)

V1.35

(V)

R

−

+

=×

(9)

For

example,

for

Rup=150kΩ

and

Rdown=51kΩ,the

−

IN START

V

is set at 5.32V.

To avoid noise, a 10nF ceramic capacitor from

EN to GND is recommended.

There is an internal Zener diode on the EN pin,

which clamps the EN pin voltage to prevent it

from running away. The maximum pull up current

assuming a worst case 12V internal Zener clamp

should be less than 1mA.

Therefore, when EN is driven by an external logic

signal, the EN voltage should be lower than 12V;

when EN is connected with VIN through a pull-up

resistor or a resistive voltage divider, the

resistance selection should ensure the maximum

pull up current less than 1mA.

If using a resistive voltage divider and VIN higher

than 12V, the allowed minimum pull-up resistor

Rup should meet the following equation:

IN

up

down

V -12V 12V

-=1mA

RR

(10)

Especially, just using the pull-up resistor Rup(the

pull-down resistor

is not

connected), the

IN-START

V

is determined by input UVLO, and the

minimum resistor value is:

IN

up

V-12V

R=

(W)

1mA

(11)

A typical pull-up resistor is 499kΩ.

Soft Start

The MP8765 employs soft start (SS) mechanism

to ensure smooth output during power-up. When

the EN pin becomes high, the internal reference

voltage ramps up gradually; hence, the output

voltage ramps up smoothly, as well. Once the

reference voltage reaches the target value, the

soft start finishes and it enters into steady state

operation.

If the output is pre-biased to a certain voltage

during startup, the IC will disable the switching of

both high-side and low-side switches until the

voltage on the internal reference exceeds the

sensed output voltage at the FB node.

Power Good (PGOOD)

The MP8765 has power-good (PGOOD) output

used to indicate whether the output voltage of the

Buck regulator is ready or not. The PGOOD pin

is the open drain of a MOSFET. It should be

a resistor (e.g. 100k). After the input voltage is

applied, the MOSFET is turned on so that the

PGOOD pin is pulled to GND before SS is ready.

After FB voltage reaches 95% of REF voltage,

the PGOOD pin is pulled high after a delay. The

PGOOD delay time is 0.5ms.

When the FB voltage drops to 85% of REF

voltage, the PGOOD pin will be pulled low.

Hiccup Over Current Protection

MP8765 has cycle-by-cycle over current limiting

control. The current-limit circuit employs a

"valley" current-sensing algorithm. The part uses

the Rds(on) of the low side MOSFET as a

current-sensing element. If the magnitude of the

current-sense signal is above the current-limit

threshold, the PWM is not allowed to initiate a

new cycle.

The trip level is fixed internally. The inductor

current is monitored by the voltage between GND

pin and SW pin. GND is used as the positive

current sensing node so that GND should be

connected to the source terminal of the bottom

MOSFET.

Since the comparison is done during the high

side MOSFET OFF and low side MOSFET ON

state, the OC trip level sets the valley level of the

inductor current. Thus, the load current at over-

follows:

Δ

OC

I

I

I _ limit

2

(12)

In an over-current condition, the current to the

load exceeds the current to the output capacitor;

thus the output voltage tends to fall off. The

Voltage (UV) threshold—typically 60% below the

reference. Once UV is triggered, the MP8765

enters hiccup mode to periodically restart the part.

This protection mode is especially useful when

the output is dead-shorted to ground, and greatly