MP5403

– CONFIGURABLE 2.7V-6V MINI PMIC WITH DUAL 2.5A/3.5A BUCK,

ONE LOAD SWITCH, AND INPUT POWER SUPERVISORY

MP5403 Rev. 1.0

www.MonolithicPower.com

17

9/20/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2016 MPS. All Rights Reserved.

Table 1: Output Discharge Conditions

Output Discharge

VIN

EN

No

>UVLO

High

Yes

>UVLO

Low

Yes

<UVLO

High

Yes

<UVLO

Low

Power Good (PG) Indicators

The MP5403 has three separate power good

(PG), open-drain, output indicators for the

regulators and load switch. For the two step-

down regulators, when FB is in the regulation

window (between 90% to 130% of the reference

voltage, 0.6V), PG1 and PG2 are pulled up to

the external bus voltage through external

resistors. The pull-up resistors are recommend

not to be too low to ensure that the leakage

current is small when the PG pins are low and

not too high if the PG pins are used to drive the

downstream signals. Normally, pull-up resistors

between

10kΩ to 400kΩ are sufficient. The PG

rising delay is around 20µs. If the FB voltage

drops below 90% or above 130% of the

reference voltage, the PG pins are pulled down

to

ground

by

an

internal

MOSFET.

The

400Ω. There is also a 60µs delay for the PG

falling threshold trigger.

The power good pin for the load switch (PG3) is

pulled high when the input voltage of the load

switch (VIN3) is higher than its UVLO threshold,

the output voltage (VOUT3) is less than 200mV

compared with the input voltage of the load

switch, and there is around 40µs of rising delay

for the PG3 indicator. If any of these three

conditions are not met, PG3 is pulled low.

The PG indicators are pulled low when VIN1 is

below UVLO. In this condition, the PG pins are

self-driven low (around 0.6V).

There is another important feature on PG to

detect the parallel capability usage (see Figure

3). After VIN rises above ULVO and either EN1

or EN2 is high, the MP5403 uses an internal

50µs detection time window to determine if the

buck regulator is entering parallel mode. The

schematic in Figure 3 is only active in the 50µs

detection window.

During this 50µs time window, the PG1 (M2)

switch is turned off, and an internal 5µA pulled

high current is applied on PG1. The PG2 (M3)

switch (<400

Ω) is turned on. If the PG1 voltage

is <150mV, the MP5403 enters parallel mode

(EN1 controls the parallel mode on/off). If the

PG1 voltage is >150mV, the MP5403 enters

independent working mode (EN1 and EN2

control separately).

Low logic enter

parallel capability

mode

VIN

PG1

PG2

Turn off PG pull

down MOSFET

during 50

Controlled by PG2

logic, if FB2 is low,

turn on MOSFET

during 50

window

0.2V clamp

voltage

0.15V compare

voltage

M1

M2

M3

OP1

OP2

V1

V2

I1

Figure 3: PG Functional Schematic

If PG1 is connected to PG2 externally, the PG1

voltage is pulled below 150mV to make the

MP5403 enter parallel mode.

The

PG1

connection

requires

special

consideration

(see

Figure

4).

If

PG1

is

connected to an

other IC’s PG to control the

other

device

together,

a

resistor

(RT)

is

required to prevent the MP5403 from entering

parallel mode. RT is suggested to be 5

0kΩ.

MP5403

PG1

Other IC

PG

External

pull up

voltage

To other

PG

control

RP

RT

Figure 4: PG Connection Example