MP3910 –PEAK CURRENT MODE BOOST CONTROLLER

MP3910 Rev. 1.11

www.MonolithicPower.com

12

11/6/2014

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OPERATION

The MP3910 uses a programmable frequency,

peak current mode architecture to regulate the

feedback voltage. The operation of the MP3910

can be understood with the block diagram of

Figure 1.

PWM Operation

At the beginning of each cycle the external N-

channel MOSFET is turned on, forcing the

current in the inductor to increase. The current

through the FET can be sensed and when the

sum voltage of amplified ISENSE signal and

slope signal rises above the voltage set by the

COMP pin, the external FET is turned off. The

inductor current then flows to the output

capacitor through the schottky diode. The

inductor current is controlled by the COMP

voltage, which itself is controlled by the output

voltage. Thus the output voltage controls the

inductor current to satisfy the load. This current

mode architecture improves transient response

and control loop stability over voltage mode

architecture.

Pulse Skipping Mode

At light load condition, the MP3910 goes into

pulse skipping mode to improve light load

efficiency. Pulse skipping decision is based on

its internal COMP voltage. If COMP is lower

than the internal sleep threshold with typical

0.95V, a PAUSE command is generated to

block the turn-on clock pulse so the power

MOSFET is turned off immediately, saving gate

driving and switching losses. This PAUSE

command also puts the whole chip into sleep

mode, consuming very low quiescent current to

further improve the light load efficiency. The

gate driver output remains low until COMP

voltage is higher than the sleep threshold, then

PAUSE signal is reset so the chip is back into

normal PWM operation.

Internal VCC Regulator

MP3910 operates with supply voltage from 7V

to 35V. An internal regulator is applied to

regulate the power at VCC pin for supplying the

internal circuitry of the controller, including the

gate driver. The regulator has a nominal output

voltage of 12V at VCC pin and must be

bypassed with no less than 1μF capacitor.

When the Enable is high, the capacitor at VCC

pin is charged through the VIN pin. VCC has its

own UVLO protection. This UVLO’s rising

threshold is 4.17V with a hysteresis of 350mV.

When the voltage at VCC pin crosses the VCC

UVLO, the controller is enabled and all the

internal circuitry is powered by VCC source. As

the

capacitor

is

charged,

VCC

voltage

increases until reaching 12V regulated voltage

if the VIN voltage is high enough.

When input voltage is lower than 12V, VCC

voltage will be lower than Vin and 12V due to

LDO drop. For normal startup, the input voltage

should be higher than 7V. If Vcc and Vin is

connected together, MP3910 can start-up from

5V but the max input voltage shouldn’t be

higher than 13 V. Vcc voltage can not be higher

than Vin voltage if both Vin and Vcc are

powered by external source because there is

one diode from Vcc to Vin.

Feedback Loop Setting

To be coincident for different design in isolated

and un-isolated application, MP3910 can

feedback the output signal through either of FB

pin or COMP pin by different setting on ISENSE

pin.

For un-isolated application such as boost mode,

MP3910 integrates one error amplifier which

can amplify the output error signal from FB pin,

COMP pin needs one RC network for

compensation. For isolated application such as

fly-back mode, the feedback signal from opto-

coupler has been amplified by secondary

circuitry, directly connect the signal to COMP

pin will make loop compensation much easier

by eliminating the primary side amplifier.

The different feedback loop can be set by

different ISENSE pin connection. At the

beginning of part enabled, ISENSE pin will

output 50us current pulse with typical value of

55uA, as showed in Figure2, if the reflected

voltage on ISENSE pin is higher than 185mV,

MP3910 will disable the internal error amplifier

between FB and COMP pins and pull up COMP