MP8869WGL datasheet(21/41 Pages) MPS

21 / 41 page

MP8869W

– 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER

MP8869W Rev. 1.02

www.MonolithicPower.com

1/18/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

regulator, including the I2C block, on and off.

Drive EN high to turn on the regulator; drive EN

low to turn off the regulator. An internal 1.5M

Ω

resistor is connected from EN to ground. EN can

operate with an 18V input voltage, which allows

EN to be directly connected to VIN for automatic

start-up. When the external EN is high, set the

EN bit to 0 in register 01 to stop the HS-FET and

LS-FET from switching. The MP8869W resumes

switching by setting the EN bit to 1.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP8869W UVLO comparator monitors the

input voltage, VIN, and output voltage of the

VCC regulator. The MP8869W is active when

the voltages exceed the UVLO rising threshold.

Soft-Start (SS) and Pre-Bias Start-Up

The soft start (SS) prevents the converter output

voltage from overshooting during start-up. When

the chip starts up, the internal circuitry generates

a soft-start voltage that ramps up from 0V to

VCC. When SS is lower than REF, the error

amplifier uses SS as the reference. When SS is

higher than REF, the error amplifier uses REF as

the reference.

The approximate typical soft-start time can be

calculated with Equation (2):

( )

(

)

()

ref







(2)

Where Vref is reference voltage of the FB loop or

I2C loop.

If the output of the MP8869W is pre-biased to a

certain voltage during start-up, the IC disables

the switching of both the HS-FET and LS-FET

until the voltage on the internal SS capacitor

exceeds the sensed output voltage at FB or

VOUT(7).

NOTE:

V_BOOT = 1, sense FB voltage. V_BOOT = 0, sense VOUT

voltage.

The MP8869W also provides a selectable soft-

stop function which defines the output discharge

behavior after EN shutdown. By default, the

output is not controlled after EN shutdown. If

setting the soft-stop control bit D[3] to 1 in

linearly to zero in a quarter of the soft-start time.

Over-Current-Protection (OCP)

The MP8869W has a default, hiccup, cycle-by-

cycle, over-current limiting control. The current-

limit circuit employs both high-side current limit

and

low-side

"valley"

current-sensing

algorithm. The part uses the RDS(ON) of the LS-

FET as a current-sensing element for the valley

current limit. If the magnitude of the high-side

current-sense signal is above the current-limit

threshold, the PWM on pulse is terminated, and

the LS-FET is turned on. Afterward, the inductor

current is monitored by the voltage between

GND and SW. GND is used as the positive

current sensing node, so GND should be

connected to the source terminal of the bottom

MOSFET. PWM is not allowed to initiate a new

cycle before the inductor current falls to the

valley threshold.

After the cycle-by-cycle over-current limit occurs,

the output voltage drops until VOUT is below the

under-voltage (UV) threshold, typically 60%

below the reference. Once UV is triggered, the

MP8869W enters hiccup mode to restart the part

periodically. This protection mode is especially

useful when the output is dead shorted to

ground. The average short-circuit current is

greatly reduced to alleviate thermal issues and

to protect the regulator. The MP8869W exits

hiccup mode once the over-current condition is

removed.

Short the output to ground first, and then power

on the part. The MP8869W’s I2C is disabled in

this condition. The I2C resumes operation after

the short circuit is removed. When hiccup OCP

bit D[1] in register 01 is set to 0 by the I2C, a

latch-off occurs if OCP is triggered, and FB UVP

is triggered.

POWER GOOD (PG)

The power good (PG) indicates whether the

output voltage is in the normal range compared

to the internal reference voltage. PG is an open-

drain structure. An external pull-up supply is

required. During power-up, the PG output is

pulled low. This indicates to the system to remain

off and keep the load on the output to a minimum.

This helps reduce in-rush current at start-up.

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