MP4575

– 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER

MP4575 Rev. 1.0

www.MonolithicPower.com

14

8/16/2016

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© 2016 MPS. All Rights Reserved.

OPERATION

The MP4575 is a step-down switching regulator

with integrated, high-voltage, power MOSFETs.

The MP4575 features a wide input voltage

range, high efficiency, external and internal soft

start,

programmable

frequency,

and

comprehensive protection modes.

Pulse-Width Modulation (PWM) Control

The MP4575 uses peak-current-mode control to

regulate the output voltage.

A PWM cycle is initiated by the internal clock at

the beginning of every cycle. After the high-side

MOSFET (HS-FET) turns on, the inductor

current rises linearly to provide energy to the

load. The HS-FET remains on until its current

the output of the internal error amplifier (EA).

The output voltage of the EA depends on the

difference of the output feedback voltage and

decides

how

much

energy

should

be

transferred to the load. The higher the load

switch is off, the low-side switch turns on, and

the inductor current flows through the low-side

switch. To prevent a shoot-through, a dead time

is inserted to prevent the HS-FET and LS-FET

from turning on at the same time. For each turn-

on and turn-off in a switching cycle, the HS-FET

remains on and off with a minimum on and off

time limit.

Light-Load Operation

The MP4575 can achieve high efficiency during

light load in two ways. First, when the load

current decreases, the inductor current drops at

same time. The LS-FET turns off to save driver

loss when the inductor current drops to zero.

Second,

when

the

load

decreases,

the

switching frequency is scaled down to reduce

threshold.

Error Amplifier (EA)

The error amplifier (EA) compares the FB

voltage with the internal reference and outputs

a current proportional to the difference between

the two. This current is used to charge the

which is used to control the HS-FET peak

current and regulate the output voltage.

Oscillator and SYNC Function

The internal oscillator frequency is set by a

single

external

resistor

connected

between FREQ and GND. The frequency-

setting resistor should be located close to the

device. The relationship between the oscillator

page 17.

During light load, the switching frequency is

below about 0.8V. Switching is disabled when

To

reduce

switching

loss

and

thermal

dissipation,

the

switching

frequency

is

decreased according to the FB voltage. When

FB is lower than 25%xREF, the switching

frequency starts to decrease from the normal

value and drops to 5% of the normal value

when FB is zero.

FREQ can be used to synchronize the internal

oscillator rising edge to an external clock falling

edge. Ensure that the high amplitude of the

synchronous (SYNC) clock is higher than 1.5V

and the low amplitude is lower than 1V to drive

the internal logic. The recommended external

SYNC frequency is in the range of 100kHz and

1MHz. There is no pulse width requirement, but

there is always a parasitic capacitance of the

pad. If the pulse width is too short, a clear rising

and falling edge may not be seen due to the

parasitic capacitance. A pulse longer than

100ns is recommended in application.

Enable (EN) Control

Enable (EN) is a control pin that turns the

regulator on and off. Drive EN higher than 1.6V

to turn on the regulator; drive EN lower than

1.3V to turn off the regulator. There is no

internal pull-up or pull-down circuitry at EN, so

when EN is floating, its status is uncertain.

EN is clamped internally using a 6.5V Zener

diode between EN and GND. Connecting EN to

a voltage source directly without any pull-up

resistor requires limiting the voltage amplitude

to ≤6V to prevent damage to the Zener diode.

EN can be connected to a higher voltage (e.g.:

VIN) through a pull-up resistor if the system