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MP4570GF датащи(PDF) 16 Page - Monolithic Power Systems |
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MP4570GF датащи(HTML) 16 Page - Monolithic Power Systems |
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16 / 22 page ![]() MP4570 – 3A, 55V, SYNCHRONOUS STEP DOWN CONVERTER MP4570 Rev. 1.01 www.MonolithicPower.com 16 1/4/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. the inductor valley current is lower than a certain current threshold which is called the valley current limit. It is very useful to avoid the inductor current to run away. Also, both the peak current limit and the valley current limit value are dependent on the FB voltage. If the feedback output voltage is higher than the 50%xREF, the current limit value is as the normal value. If the feedback output voltage is lower than 50%xRFF, the current limit will decrease and drop to the half normal value when the feedback output voltage is zero. This feature is very helpful to reduce the OCP thermal dissipation which may especially get worse when the output voltage is shorted. Also, it is very helpful to reduce the high inrush current during the startup. UVLO Protection The MP4570 has input under voltage lockout protection (UVLO). Assuming the EN is active, the MP4570 is powered on when the input voltage is higher than the UVLO rising threshold and is powered off when input voltage drops below the UVLO falling threshold. Thermal Shutdown Protection The thermal shutdown is employed in MP4570 by monitoring the IC temperature internally. If the junction temperature exceeds the threshold (typically 170oC), the regulator shuts off and it will turns on again when the temperature drops below 160oC. There is a ~10oC hysteresis. Power Good MP4570 has one power good (PG) pin out to indicate the normal operation after soft start time. The PG pin is the open drain of an internal MOSFET. It should be connected to VDD or external voltage source through a resistor (i.e. 100kohm). After the input voltage is applied, the MOSFET is turned on and the PG pin is pulled to GND before SS is ready. After the FB voltage reaches 90% REF voltage, the MOSFET turns off and PG pin is pulled to high by external voltage source. When the FB voltage drops to 85% REF voltage, the PG voltage is pulled to GND to indicate a failure output status. Floating Driver and Bootstrap Charging An external bootstrap capacitor (0.1µF typically) between BST pin and SW pin powers the floating power MOSFET driver. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.3V with a hysteresis of 300mV. The driver’s UVLO is soft-start related: When the bootstrap voltage hits its UVLO threshold, the soft-start circuit resets. When bootstrap UVLO is gone, the reset is off and then the soft-start process resumes. The dedicated internal bootstrap regulator regulates and charges the bootstrap capacitor to 4.2V. When the voltage between the BST and SW nodes is less than its regulation, a PMOS pass transistor from VIN to BST turns ON. The charging current path is from VIN, BST and then to SW. As long as VIN is sufficiently higher than VSW, the bootstrap capacitor can be charged. When the high side MOSFET is ON, VIN≈VSW so the bootstrap capacitor can’t be charged. When low side MOSFET is ON, the difference between VIN and VSW is at its largest, thus making it the best period to charge. When there is no current in the inductor, VSW=VOUT so the difference between VIN and VOUT can charge the bootstrap capacitor. At higher duty cycles, the time period available for bootstrap charging is shorter so the bootstrap capacitor may not be sufficiently charged. If the internal circuit does not have sufficient voltage and the bootstrap capacitor is not charged, extra external circuitry can be used to ensure the bootstrap voltage is within the normal operational region. |
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