| поискавой системы для электроныых деталей |
|
MP2918GL датащи(PDF) 24 Page - Monolithic Power Systems |
|
|
|||||||||||||||||||||||||||||
MP2918GL датащи(HTML) 24 Page - Monolithic Power Systems |
|
24 / 30 page ![]() MP2918 —4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER MP2918 Rev. 1.02 www.MonolithicPower.com 24 5/31/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. The system has two important poles: one from the compensation capacitor (C6) and the output resistor of the error amplifier, and the other from the output capacitor and the load resistor (see Figure 9). These poles can be calculated with Equation (16) and Equation (17): m P1 O G f 2 π C6 A (16) LOAD P2 R Co 2 π 1 f (17) Where Gm is the error amplifier transconductance (500 μA/V), and Co is the output capacitor. The system has one important zero due to the compensation capacitor and the compensation resistor (R5), which can be calculated with Equation (18): Z1 1 f 2 π C6 R5 (18) The system may have another significant zero if the output capacitor has a large capacitance or high ESR value and can be calculated with Equation (19): ESR ESR R Co 2 π 1 f (19) In this case, a third pole set by the compensation capacitor (C7) and the compensation resistor can compensate for the effect of the ESR zero. This pole is calculated with Equation (20): P3 1 f 2 π C7 R5 (20) The goal of the compensation design is to shape the converter transfer function for a desired loop gain. The system crossover frequency where the feedback loop has unity gain is important, since lower crossover frequencies result in slower line and load transient responses, and higher crossover frequencies lead to system instability. Set the crossover frequency to ~0.1 x fSW. Follow the steps below to design the compensation. 1. Choose R5 to set the desired crossover frequency with Equation (21): C OUT m CS FB 2 π Co f V R5 G G V (21) Where fC is the desired crossover frequency. 2. Choose C6 to achieve the desired phase margin. For applications with typical inductor values, set the compensation zero (fZ1) <0.25 x fC to provide a sufficient phase margin. C6 is then calculated with Equation (22): C 4 C6 2 π R5 f (22) 3. C7 is required if the ESR zero of the output capacitor is located at <0.5 x fSW, or Equation (23) is valid: 2 f R Co 2 π 1 SW ESR (23) If this is the case, use C7 to set the pole (fP3) at the location of the ESR zero. Determine C7 with Equation (24): ESR Co R C7 R5 (24) |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |