MP2918

—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER

MP2918 Rev. 1.02

www.MonolithicPower.com

20

5/31/2017

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EN/SYNC Control

The

MP2918

has

a

dedicated

enable

(EN/SYNC)

control

that

uses a bandgap-

generated precision threshold of 1.22V. By

pulling EN/SYNC high or low, the IC can be

enabled or disabled. To disable the part,

EN/SYNC must be pulled low for at least 40µs.

threshold

(see

Figure

4).

The

EN/SYNC

UVLO threshold is 1.09V x (1 + R16/R17).

pull-up resistor is needed to prevent EN/SYNC

from breaking down.

EN/

SYNC

VIN

R16

R17

Figure 4: EN/SYNC Resistor Divider

Synchronize

The MP2918 can be synchronized to an

external clock ranging from 100kHz up to

1000kHz through EN/SYNC. The internal clock

rising edge is synchronized to the external clock

rising edge. The pulse width (both on and off) of

the external clock signal should be no less than

100ns.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) is implemented

to protect the chip from operating at an

insufficient input supply voltage. The MP2918

UVLO rising threshold is about 4.5V, while its

falling threshold is a consistent 3.7V.

Thermal Protection

Thermal protection prevents damage to the IC

from

excessive

temperatures.

The

die

temperature is monitored internally until the

thermal limit is reached. When the silicon die

temperature is higher than 170°C, the entire

chip shuts down. When the temperature is

lower than its lower threshold (typically 20°C),

the chip is enabled again.

Start-Up and Shutdown

respective thresholds, the chip starts up. The

reference block starts first, generating stable

reference voltages and currents. The internal

regulator

is

then

enabled.

The

regulator

provides a stable supply for the remaining

circuitries.

Three

events

can

shut

down

the

chip:

During the shutdown procedure, the signal path

is blocked first to avoid any fault triggering.

pulled down. The floating driver is not subject to

this shutdown command.

Pre-Bias Start-Up

If SS is less than FB at start-up, the output has

a pre-bias voltage, and neither TG nor BG is

turned on until SS is greater than FB.