MP2233 – SYNCHRONOUS, STEP-DOWN CONVERTER WITH INTERNAL MOSFETS

MP2233 Rev. 1.01

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14

12/6/2012

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Selecting the Output Capacitor

The output capacitor (C2) maintains the DC

output voltage. Use ceramic, tantalum, or low-

ESR

electrolytic

capacitors.

Low

ESR

capacitors are preferred to keep the output

voltage ripple low. The output voltage ripple can

be estimated by:

OUT

OUT

OUT

ESR

S1

IN

S

VV

1

V1

R

fL

V

8 f

C2

⎛⎞

⎛⎞

Δ=

× −

×

+

⎜⎟

⎜⎟

×× ×

⎝⎠ ⎝⎠

equivalent series resistance of the output

capacitor.

For

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency. The capacitance also causes the

majority of the output voltage ripple. For

simplification, estimate the output voltage ripple

as:

OUT

OUT

OUT

2

IN

S1

VV

ΔV1

V

8f

L

C2

⎛⎞

=× −

⎜⎟

×× ×

⎝⎠

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated as:

OUT

OUT

OUT

ESR

IN

S1

VV

ΔV1

R

fL

V

⎛⎞

=× −

×

⎜⎟

×

⎝⎠

The characteristics of the output capacitor also

affect the stability of the regulation system. The

MP2233 can be optimized for a wide range of

capacitance and ESR values.

External Bootstrap Diode

An external bootstrap diode can enhance the

efficiency of the regulator, given the following

conditions:

Duty cycle is high: D=

IN

OUT

V

V

>65%

In these cases, connect an external BST diode

from the VCC pin to BST pin, as shown in

Figure 6.

MP2233

Figure 6: Optional External Bootstrap Diode to

Enhance Efficiency

The recommended external BST diode is

IN4148, and the BST capacitor is 0.1µF to 1μF.

PCB layout is very important to achieve stable

operation especially for VCC capacitor and

input capacitor placement. For best results,

follow these guidelines:

1) Directly connect the GND pin to a large

ground plane. Add vias near the GND pin if

the bottom layer is a ground plane.

2) Place the VCC capacitor as close to the

VCC and GND pins as possible. Make the

trace

length

of

the

VCC

pin→VCC

capacitor anode VCC capacitor cathode→

IC GND pin as short as possible.

3) Place the ceramic input capacitor close to

IN and GND pins. Keep the connection of

input capacitor and IN pin as short and

wide as possible.

4) Route SW, BST net away from sensitive

analog areas such as FB. Avoid routing the

SW, BST trace under the IC.

5) Place the T-type feedback resistor (R5)

close to chip to ensure that the trace to the

FB pin is as short as possible.

Notes:

8) The recommended layout is based on the Figure 7 Typical

Application circuit on the next page.