MP2233 – SYNCHRONOUS, STEP-DOWN CONVERTER WITH INTERNAL MOSFETS

MP2233 Rev. 1.01

www.MonolithicPower.com

10

12/6/2012

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OPERATION

The MP2233 is a high-frequency, synchronous,

rectified, step-down, switch-mode converter

with built-in power MOSFETs. It offers a very

compact solution to achieve a continuous 3A

output current with excellent load and line

regulation over a wide input supply range.

The MP2233 operates in a fixed-frequency,

peak-current–control mode to regulate the

output voltage. The internal clock initiates a

PWM cycle. The integrated high-side power

MOSFET turns on and remains on until its

current reaches the value set by the COMP

voltage. When the power switch is off, it

remains off until the next clock cycle starts. If

the current in the power MOSFET does not

reach the COMP set current value within 89%

of one PWM period, the power MOSFET will be

forced to turn off. The high-side power

MOSFET has an 80ns minimum off time to

refresh the BST voltage.

Internal Regulator

The 5V internal regulator powers most of the

output decreases and requires a 0.1µF ceramic

decoupling capacitor.

Error Amplifier

The error amplifier compares the FB pin voltage

outputs a current proportional to the difference

between the two. This output current then

charges

or

discharges

the

internal

compensation network to form the COMP

voltage, which controls the power MOSFET

current. The optimized internal compensation

network minimizes the external component

counts and simplifies the control loop design.

Enable/SYNC Control

EN is a digital control pin that turns the

regulator on and off. Drive EN high to turn on

the regulator, drive it low to turn it off after a 5μs

delay. An internal 1MΩ resistor from EN to

GND allows EN to float to shut down the chip.

The EN pin is clamped internally using a 6.5V

series-Zener-diode as shown in Figure 2.

Connecting the EN pin through a pullup resistor

input current to less than 100µA.

Connecting the EN pin directly to a voltage

source without any pull-up resistor requires

limiting the amplitude of the voltage source to

below 6.5V to prevent damaging the Zener

diode.

EN/SYNC

EN LOGIC

GND

Zener

6.5V-typ

Figure 2: Zener Diode Circuit

For external clock synchronization, connect a

clock with a frequency range of 300kHz to

3MHz after setting the output voltage: The

internal clock’s rising edge will synchronize with

the external clock’s rising edge. Select an

external clock signal with a pulse-width less

than 700ns.

Under-Voltage Lockout

The MP2233 has under-voltage lock-out (UVLO)

protection. When VCC exceeds the UVLO

rising threshold voltage, the MP2233 powers up.

It shuts off when VCC falls below the UVLO

falling threshold voltage. This is non-latch

protection.

The MP2233 is disabled when the input voltage

falls below 3.25 V. If an application requires a

higher UVLO, use the EN pin as shown in

Figure 3 to adjust the input voltage UVLO by

using two external resistors. For best results,

use the enable resistors to set the UVLO falling

threshold (VSTOP) above 4.5V. The rising

threshold (VSTART) should be set to provide