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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16F818-E/ML датащи(PDF) 16 Page - Microchip Technology |
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PIC16F818-E/ML датащи(HTML) 16 Page - Microchip Technology |
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16 / 176 page  PIC16F818/819 DS39598E-page 14 2004 Microchip Technology Inc. Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17, 54 82h(1) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23 83h(1) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 16 84h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 23 85h TRISA TRISA7 TRISA6 TRISA5(3) PORTA Data Direction Register (TRISA<4:0> 1111 1111 39 86h TRISB PORTB Data Direction Register 1111 1111 43 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 23 8Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18 8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 19 8Dh PIE2 — — — EEIE — — — — ---0 ---- 21 8Eh PCON — — — — — —POR BOR ---- --qq 22 8Fh OSCCON — IRCF2 IRCF1 IRCF0 — IOFS — — -000 -0-- 38 90h(1) OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 36 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 68 93h SSPADD Synchronous Serial Port (I2C™ mode) Address Register 0000 0000 71, 76 94h SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 72 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 81 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 82 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’. |
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