PIC16F818-ESLASHML datasheet(41/176 Pages) MICROCHIP

41 / 176 page

 2004 Microchip Technology Inc.

DS39598E-page 39

PIC16F818/819

5.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the

“PICmicro®

Mid-Range

MCU

Family

Reference

Manual” (DS33023).

5.1

PORTA and the TRISA Register

PORTA is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISA bit (= 0)

will make the corresponding PORTA pin an output (i.e.,

put the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified and then written to the port

data latch.

Pin RA4 is multiplexed with the Timer0 module clock

input and with an analog input to become the RA4/AN4/

T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt

Trigger input and full CMOS output driver.

Pin RA5 is multiplexed with the Master Clear module

input. The RA5/MCLR/VPP pin is a Schmitt Trigger input.

Pin RA6 is multiplexed with the oscillator module input

and external oscillator output. Pin RA7 is multiplexed

with the oscillator module input and external oscillator

input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI

are Schmitt Trigger inputs and full CMOS output drivers.

Pins RA<1:0> are multiplexed with analog inputs. Pins

RA<3:2> are multiplexed with analog inputs and VREF

inputs. Pins RA<3:0> have TTL inputs and full CMOS

output drivers.

EXAMPLE 5-1:

INITIALIZING PORTA

TABLE 5-1:

PORTA FUNCTIONS

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Note:

Power-on

Reset,

the

pins

PORTA<4:0> are configured as analog

inputs and read as ‘0’.

BANKSEL

PORTA

; select bank of PORTA

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

BANKSEL

ADCON1

; Select Bank of ADCON1

MOVLW

0x06

; Configure all pins

MOVWF

ADCON1

; as digital inputs

MOVLW

0xFF

; Value used to

; initialize data

; direction

MOVWF

TRISA

; Set RA<7:0> as inputs

Name

Bit#

Buffer

Function

RA0/AN0

bit 0

TTL

Input/output or analog input.

RA1/AN1

bit 1

TTL

Input/output or analog input.

RA2/AN2/VREF-

bit 2

TTL

Input/output, analog input or VREF-.

RA3/AN3/VREF+

bit 3

TTL

Input/output, analog input or VREF+.

RA4/AN4/T0CKI

bit 4

Input/output, analog input or external clock input for Timer0.

RA5/MCLR/VPP

bit 5

Input, Master Clear (Reset) or programming voltage input.

RA6/OSC2/CLKO

bit 6

Input/output, connects to crystal or resonator, oscillator output or 1/4 the

frequency of OSC1 and denotes the instruction cycle in RC mode.

RA7/OSC1/CLKI

bit 7

ST/CMOS(1) Input/output, connects to crystal or resonator or oscillator input.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1:

This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other Resets

05h

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

xxx0 0000

uuu0 0000

85h

TRISA

TRISA7 TRISA6 TRISA5(1) PORTA Data Direction Register

1111 1111

9Fh

ADCON1

ADFM

ADCS2

—

PCFG3 PCFG2 PCFG1

PCFG0

00-- 0000

Legend:

= unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note

Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.

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