S29AS016J datasheet(11/59 Pages) CYPRESS

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Document Number: 002-01122 Rev.*L

Page 11 of 59

S29AS016J

7.1

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is

set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by

CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

7.2

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the

device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines

whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no

spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the

device data outputs. The device remains enabled for read access until the command register contents are altered.

See Reading Array Data on page 27 for more information. Refer to the AC Read Operations on page 44 for timing specifications and

to Figure 18.1 on page 44 for the timing diagram. ICC1 in DC Characteristics on page 42 represents the active current specification

for reading array data.

7.3

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the

system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word/Byte

Configuration on page 11 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,

only two write cycles are required to program a word or byte, instead of four. Word/Byte Program Command Sequence on page 28

has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 13 and Table on page 15 indicate

the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector.

The Command Definitions on page 27 has details on erasing a sector or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to Autoselect Mode on page 12 and Autoselect Command Sequence on page 27 for more information.

ICC2 in DC Characteristics on page 42 represents the active current specification for the write mode. AC Characteristics on page 44

contains timing specification tables and timing diagrams for write operations.

7.4

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0.

Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 36 for more information, and

to AC Characteristics on page 44 for timing diagrams.

7.5

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current

consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC  0.2 V. (Note that this is a more

restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC  0.2 V, the device will be in the standby

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