EMC6D103 datasheet(73/89 Pages) SMSC

73 / 89 page

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

SMSC EMC6D103

Revision 0.4 (04-04-05)

DATASHEET

■

TACH1, TACH2, TACH3, TACH4

■

PWM2, PWM3

Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL

are not included in the test tree.

8.2.22

This is a read/write register. Writing this register may produce unwanted results.

This register becomes read only when the Lock bit is set. Any further attempts to write to this register

shall have no effect.

8.2.23

This is a read/write register. Writing this register may produce unwanted results.

8.2.24

This is a read/write register. Writing this register may produce unwanted results.

These registers become read only when the Lock bit is set. Any further attempts to write to these

registers shall have no effect.

8.2.25

This register becomes read only when the Lock bit is set. Any further attempts to write to this register

shall have no effect.

Table 8.39 Register 79h: SMSC Test Register

Address

Read/

Write

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

79h

R/W

SMSC Test Register

TST7

TST6

TST5

TST4

TST3

TST2

TST1

TST0

00h

Table 8.40 Register 7Ah: SMSC Test Register

Address

Read/

Write

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

7Ah

SMSC Test Register

RES

TST6

TST5

TST4

TST3

TST2

TST1

TST0

00h

Table 8.41 Register 7Bh: SMSC Test Register

Address

Read/

Write

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

7Bh

R/W

SMSC Test Register

TST7

TST6

TST5

TST4

TST3

TST2

TST1

TST0

00h

Table 8.42 Register 7Ch: Special Function Register

Address

Read/

Write

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

7Ch

R/W

Special Function

AVG2

AVG1

AVG0

SMSC

INTEN

MONMD

LPMD

40h

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