EMC6D103 datasheet(70/89 Pages) SMSC

70 / 89 page

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

Revision 0.4 (04-04-05)

SMSC EMC6D103

DATASHEET

8.2.18

Registers 64-66h: Minimum PWM Duty Cycle

These registers become read only when the Lock bit is set. Any further attempts to write to these

registers shall have no effect.

These registers specify the minimum duty cycle that the PWM will output when the measured

temperature reaches the Temperature LIMIT register setting in Auto Fan Control Mode.

Table 8.31 PWM Ramp Rate Control

RRX-[2:0]

PWM RAMP TIME

(SEC)

(TIME FROM 33%

DUTY CYCLE TO

100% DUTY CYCLE)

PWM RAMP TIME

(SEC)

(TIME FROM 0%

DUTY CYCLE TO

100% DUTY CYCLE)

TIME PER PWM STEP

(PWM STEP SIZE =

1/255)

PWM

RAMP RATE

(HZ)

000

52.53

206 msec

4.85

001

17.6

26.52

104 msec

9.62

010

11.8

17.595

69 msec

14.49

011

7.0

10.455

41 msec

24.39

100

4.4

6.63

26 msec

38.46

101

3.0

4.59

18 msec

55.56

110

1.6

2.55

10 msec

100

111

0.8

1.275

5 msec

200

Table 8.32 Registers 64-66h: Minimum PWM Duty Cycle

Address

Read/

Write

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

64h

R/W

PWM1 Minimum Duty Cycle

80h

65h

R/W

PWM2 Minimum Duty Cycle

80h

66h

R/W

PWM3 Minimum Duty Cycle

80h

Table 8.33 PWM Duty vs. Register Setting

MINIMUM PWM DUTY

VALUE (DECIMAL)

VALUE (HEX)

00h

25%

40h

50%

128

80h

100%

255

FFh

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