HARDWARE-BASED WRITE PROTECTION

You can also write-protect the entire memory area of the 24LLC02. This method of write protection is controlled

by the state of the Write Protect (WP) pin.

The 24LLC02 will acknowledge slave and word address, but it will not generate an acknowledge after receiving

the first byte of the data. Thus the write cycle will not be started when the stop condition is generated . By

These write protection features effectively change the EEPROM to a ROM in order to prevent data from being

overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on

the bus, but data bytes are not acknowledged.

CURRENT ADDRESS BYTE READ OPERATION

The internal word address pointer maintains the address of the last word accessed, incremented by one.

Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access

data at address “n+1”.

bits of data.The master does not acknowledge the transfer but it does generate a Stop condition. In this way,

the 24LLC02 effectively stops the transmission (see Figure 1-12).

Slave Address

Data

Start

A

C

K

Stop

N

O

A

C

K

Figure 1-12. Current Address Byte Read Operation

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: server@ceramate.com.tw

Tel:886-3-3529445

Http: www.ceramate.com.tw

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Rev 1.2 May 6,2002

24LLC02

2K-bit Serial EEPROM for Low Power