24LLC02A datasheet(5/19 Pages) ETC

5 / 19 page

FUNCTION DESCRIPTION

2C-BUS INTERFACE

The

24LLC02 supports the I 2C-bus serial interface data transmission protocol. The two-wire bus consists of a

serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V CC by a

pull-up resistor that is located somewhere on the bus.

Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus

is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions

, controlling bus access. Using the A0, A1, and A2 input pins, up to eight

24LLC02 devices can be connected

to the same I

2 C-bus as slaves (see Figure 1-6). Both the master and slaves can operate as transmitter or receiver

, but the master device determines which bus operating mode would be active.

SDA

Bus Master

(Transmitter/

Receiver)

MCU

2 4 2 LL C

Tx/Rx

A0 A1 A2

Slave 1

To V CC or V SS

Tx/Rx

A0 A1 A2

Slave 2

To V CC or V SS

Tx/Rx

A0 A1 A2

Slave 3

To V CC or V SS

Tx/Rx

A0 A1 A2

Slave 8

To V CC or V SS

VCC

V CC

SCL

Figure 1-6. Typical Configuration (16 Kbits of Memory on the I

2 C-Bus)

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Email: server@ceramate.com.tw

Tel:886-3-3529445

Http: www.ceramate.com.tw

Fax:886-3-3521052

Page

5 of 19

Rev 1.2 May 6,2002

24LLC02

2K-bit Serial EEPROM for Low Power

24LLC02

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