S71PL254 datasheet(25/196 Pages) SPANSION

25 / 196 page

Publication Number S29PL127J_064J_032J_MCP

Revision A Amendment 3 Issue Date August 12, 2004

ADVANCE

INFORMATION

S29PL127J/S29PL064J/S29PL032J for MCP

128/64/32 Megabit (8/4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIOTM Control

Distinctive Characteristics

Architectural Advantages

128/64/32 Mbit Page Mode devices

— Page size of 8 words: Fast page read access from

random locations within the page

Single power supply operation

— Full Voltage range: 2.7 to 3.1 volt read, erase, and

program operations for battery-powered applications

Simultaneous Read/Write Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

FlexBank Architecture (PL127J/PL064J/PL032J)

— 4 separate banks, with up to two simultaneous

operations per device

—Bank A:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

—Bank B:

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

—Bank C:

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

—Bank D:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

Enhanced VersatileI/OTM (VIO) Control

— Output voltage generated and input voltages

tolerated on all control inputs and I/Os is determined

by the voltage on the VIO pin

—VIO options at 1.8 V and 3 V I/O for PL127J devices

—3V VIO for PL064J and PL032J devices

Secured Silicon Sector region

— Up to 128 words accessible through a command

sequence

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

Both top and bottom boot blocks in one device

Manufactured on 110 nm process technology

Data Retention: 20 years typical

Cycling Endurance: 1 million cycles per sector

typical

Performance CharacteristicS

High Performance

— Page access times as fast as 20 ns

— Random access times as fast as 55 ns

Power consumption (typical values at 10 MHz)

— 45 mA active read current

— 17 mA program/erase current

— 0.2 µA typical standby mode current

Software Features

Software command-set compatible with JEDEC

42.4 standard

— Backward compatible with Am29F, Am29LV,

Am29DL, and AM29PDL families and MBM29QM/RM,

MBM29LV, MBM29DL, MBM29PDL families

CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

Erase Suspend / Erase Resume

— Suspends an erase operation to allow read or

program operations in other sectors of same bank

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

S71PL254 датащи(PDF) 25 Page - SPANSION

S71PL254 датащи(HTML) 25 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL