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LTC4212CMS датащи(PDF) 18 Page - Linear Technology |
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LTC4212CMS датащи(HTML) 18 Page - Linear Technology |
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18 / 24 page ![]() 18 LTC4212 4212f OPERATIO Figure 4. Power-Up with Overcurrent, Slow Comparator Trips the Circuit Breaker VCC VCC ON VREF 2.34V VREF TIMER GATE DC/DC CONVERTER OUTPUT VCC – VSENSE FAULT PGT PGI PGF 4212 F04 12 3 4 5 6 7 8 9 10 11 13 12 1415 16 POWER GOOD TIMER ENABLED (CPGT) 0.95V 0.65V 2ND TIMING CYCLE (CTIMER) 1ST TIMING CYCLE (CTIMER) 1ST TIMING CYCLE (CTIMER) SOFT-START ACTIVE VREF VCC – VSENSE = 50mV > 50mV, >18 µs It consists of the time the FAULT pin takes to discharge CAUTO (Time Points 9 to 10), the 120µs needed to reset the circuit breaker (Time Points 9 to 11), the time it takes the pull-up resistor at the ON pin to charge CAUTO above 1.316V (Time Points 11 to 12) and the elapsed time before the external N-channel starts to conduct during the second timing cycle (Time Points 12 to 16). Sense Resistor Considerations The fault current level at which the LTC4212’s internal electronic circuit breaker trips is determined by a sense resistor connected between the LTC4212’s VCC and SENSE pins and two separate trip points. The first trip point is set |
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